Scheduling hardware generated by high level language...

Details Scheduling hardware generated by high level language... Scheduling hardware generated by high level language...

2006-09-19

2006-09-19

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07111274

ABSTRACT:
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (100) and identifying data input to each component specified in the language independent model to determine a latency for each component (220, 225). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (230). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself (235).

REFERENCES:
patent: 6044211 (2000-03-01), Jain
U.S. Appl. No. 10/310,336, filed Dec. 4, 2002, Edwards et al.
U.S. Appl. No. 10/310,362, filed Dec. 4, 2002, Edwards et al.
U.S. Appl. No. 10/310,520, filed Dec. 4, 2002, Miller et al.

Affiliated with

Also associated with

Rating

Scheduling hardware generated by high level language... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scheduling hardware generated by high level language..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scheduling hardware generated by high level language... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3553675