Scheduler, method and program for scheduling, and apparatus...

Details Scheduler, method and program for scheduling, and apparatus... Scheduler, method and program for scheduling, and apparatus...

2007-02-20

2007-02-20

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10887801

ABSTRACT:
A scheduler includes: a schedule information acquisition section configured to acquire the number of first clock cycles and the number of second clock cycles as schedule information of a function belonging to a lower-hierarchy, the number of the first clock cycles being the number of clock cycles after an execution of the function is started until an input data of the function is used, the number of the second clock cycles being the number of clock cycles after an output data of the function is outputted until the execution of the function is completed; and a scheduling processing section configured to obtain operations executable in the first clock cycles and operations executable in the second clock cycles from among operations belonging to an upper-hierarchy for calling the function, based on the acquired schedule information, and to schedule the upper-hierarchy ensure that the obtained operations execute in parallel with the function.

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Daniel D. Gajski, Nikil D. Dutt, Allen C-H Wu, and Steve Y-L Lin, “High-Level Synthesis Introduction to Chip and System Design”, Kluwer Academic Publishers, 1992, pp. 213-255.

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