Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-15
2003-08-19
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000, C703S015000, C707S793000
Reexamination Certificate
active
06609227
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to Very Large Scale Integration (VLSI) Schematic design program scheduling method that allows a designer to submit and execute multiple VLSI Schematic design program jobs in an automated fashion.
BACKGROUND INFORMATION
Schematic generation in VLSI design is that part of the design process where the Logic and Logic interconnections are designed to implement a particular system function. The Schematic describes the logic blocks and how their inputs and outputs are connected to make various functions and ultimately an entire VLSI chip What kind of and how many devices (e.g., transistors) are required to make a given function (e.g., AND gate) may not be important to the Logic of the function relative to the Schematic.
In this phase of the VLSI design process, noise, power, actual wiring structure, delay, and etc. are not necessarily considered. There are various details in this phase of the design that affect the Logic functionality (realizing the desired function) and there are other details (e.g., device sizes, transistor types, labels, etc.) that are important but do not affect the Logic functionality of the design. Logic functionality may be represented simply by “Logic” throughout this disclosure.
Typically there are several VLSI Schematic design programs (jobs) that are run to complete and verify a VLSI design. A designer may submit the jobs in sequence or in parallel. When the designer submits the design jobs in sequence, typically errors encountered in running the first design job (program) are corrected and that job is rerun until it is error free. Outputs from the first design job are then applied to the next applicable design job. This process is continued until the VLSI Schematic design is complete. If the jobs are run in parallel, then several design jobs are launched simultaneously. In the parallel mode, the designer may have to determine whether to abort other jobs still running when a design job fails. Aborting incomplete jobs may be appropriate when it is known the failing job also indicates probable errors in the incomplete job. In other instances, a job may fail for reasons that do not adversely affect incomplete jobs and therefore these jobs may be allowed to run until completion. Regardless, the designer would have to continually take action and may have to restart several jobs to keep the VLSI design process going until all jobs complete successfully.
It is useful to review the present VLSI design job environment. In a part of the VLSI design a Schematic, which represents a desired system Logic, is generated and verified by various Schematic design and checking programs. The following describes programs which may be used to explain embodiments of the present invention:
Gatemaker—generates models and verifications of the test view
VIM—generates circuit features, inputs/outputs, transistor models, etc.
VHDL—is a high level description language view of the design
Schematic—is the circuitry diagram
Cosmetic Error Programs—programs that keep unchanged the results of schematic based programs (the data defining the Schematic itself) while updating other descriptive data.
To describe the Schematic design process, assume that the VHDL of the Schematic macro has been completed. After the Schematic is checked and saved, the VIM of the macro is generated from data in the Schematic database. At this time, the designer may run a VHDL versus Schematic checking program. On the other hand, the Gatemaker program may also be run. Gatemaker in this example comprises two steps:
1. generate the test view (Gatemaker Model) of the Schematic.
2. Validation of models
a) generate the test patterns and apply that to the test view to generate the response,
b) apply the same test patterns to Schematic view to generate the response,
c) compare those two responses to see if they are the same.
After the generation of Gatemaker Model, the VHDL versus Gatemaker Model has enough inputs to do the verification. Normally, the designer discretely and manually submits these jobs in series. Submitting the VLSI Schematic design jobs may be very sequential, step-by-step, and done manually. The whole process depends on the actions of an individual designer. The designer has to keep track of multiple jobs and know which jobs to re-submit and which jobs have valid results. This takes up valuable time the designer may use for other design tasks.
Because of this there is a need for a VLSI Schematic design job scheduler that would relieve the designer of any tasks except correcting errors and re-starting the design process wherein a design job scheduler decides which programs need to be re-run and what results may be used for executing subsequent jobs.
SUMMARY OF THE INVENTION
A Schematic is generated by creating functional Logic by interconnecting library logic blocks or interconnection library macro logic blocks until it is believed that the desired function has been implemented successfully. Within a Schematic various logic blocks may require the resizing of transistors within a logic block depending on fan out requirements, speed or other requirements. While these considerations are important they may not be pertinent to the Logic represented by the Schematic. Data defining a Schematic is generated, checked and saved as the starting database. A scheduler program launches several Schematic design programs in parallel. One of the programs is a checking program that extracts and separates data from the Schematic entry that is related to the Logic of the Schematic and data that is not related to the Logic. Since initially the data has not been changed, the checking program awaits results of the first pass of Schematic program execution. The first pass will generate a Schematic which may or may not have errors. When the Schematic data is updated the Schematic design programs are re-launched. If the changes are not related to the Logic then a previously generated result data regarding the Logic may not have to be re-run and the uncompleted “Logic related” programs may be stopped. However, if the changes are related to Logic then the programs are allowed to run to completion and the resulting errors noted and corrected by the designer. As the design process nears completion, when the changes are most likely cosmetic, then long running Logic programs are not re-run and their results remain as release data.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5526517 (1996-06-01), Jones et al.
patent: 5862149 (1999-01-01), Carpenter et al.
patent: 6324678 (2001-11-01), Dangelo et al.
Bushnell et al., Mar. 1989, Computer-Aided Design of Integrated Circuit and Systems, IEEE Transactio, 8 Issue, pp. 279-287.
Bradley Douglas Hooker
Cao Tai Anh
Frankeny Richard F.
International Business Machines - Corporation
Rossoshek Yelena
Salys Casimer K.
Winstead Sechrest & Minick P.C.
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