Scheduler for a direct memory access device having multiple...

Details Scheduler for a direct memory access device having multiple... Scheduler for a direct memory access device having multiple...

2007-08-07

2007-08-07

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S028000, C710S005000, C710S006000, C710S052000, C710S054000

Reexamination Certificate

active

09740669

ABSTRACT:
A scheduler configured to schedule multiple channels of a Direct Memory Access (DMA) device includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also includes a weight that is determined based on these multiple fields. The scheduler also includes a comparison-logic circuit that is configured to then sort the entries based on their respective weights.

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patent: 6052375 (2000-04-01), Bass et al.

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