Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-09-29
2010-11-30
Tsai, Henry W. (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C370S412000
Reexamination Certificate
active
07844760
ABSTRACT:
A method and apparatus for schedule and data caching for wireless transmissions. An embodiment of a method may include generating a schedule of queues for a wireless controller, the schedule being generated at a driver on a host system. In some embodiments schedule data may be cached at the wireless controller from the host system, where the cache may include active queues and page list entries for the active queues. The wireless controller may be operated using the cached queues.
REFERENCES:
patent: 2004/0015504 (2004-01-01), Ahad et al.
patent: 2005/0286544 (2005-12-01), Kitchin et al.
Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0, Intel Corporation, Mar. 12, 2002.
Wireless Host Controller Interface Specification for Certified Wireless Universal Serial Bus, Revision 0.95, Intel Corporation, Jun. 16, 2006.
SIPO People's Republic of China, Office Action for Chinese Patent Application No. 200810177871.5 mailed Feb. 12, 2010.
Hiremath Indudharswamy
Jeyaseelan Jaya L.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nam Hyun
Tsai Henry W.
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