Scavenging metal stack for a high-k gate dielectric

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S411000, C257SE21625

Reexamination Certificate

active

07989902

ABSTRACT:
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

REFERENCES:
patent: 2004/0185198 (2004-09-01), Sisson et al.
patent: 2010/0187643 (2010-07-01), Chudzik et al.
Hubbard et al., “Thermodynamic stability of binary oxides in contact with silicon”, J. Mater. Res. vol. 11, No. 11, Nov. 1996, pp. 2757-2776.

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