Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-17
2009-11-03
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07614030
ABSTRACT:
A method for reducing ESD on scattering bars in forming a mask containing a target pattern is provided. In one embodiment, the target pattern comprising features to be imaged onto a substrate is obtained. The mask is modified to include at least one scattering bar, the at least one scattering bar being placed adjacent to edges of the features to be imaged. Thereafter, the scattering bar is truncated into one or more scattering bar segments by determining an optimized length for each of the one or more scattering bar segments, wherein ESD on the one or more scattering bar segments is substantially reduced.
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TW Office Action mailed Jul. 8, 2009.
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
Whitmore Stacy A
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