Scanning imager employing multiple chips with staggered pixels

Details Scanning imager employing multiple chips with staggered pixels Scanning imager employing multiple chips with staggered pixels

2006-10-30

2009-06-30

Pyo, Kevin (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C348S275000, C348S302000, C257S292000

Reexamination Certificate

active

07554067

ABSTRACT:
A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).

REFERENCES:
patent: 6084229 (2000-07-01), Pace et al.
patent: 6166831 (2000-12-01), Boyd et al.
patent: 6707067 (2004-03-01), Zhong et al.
patent: 2007/0014019 (2007-01-01), Mouli

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