Scannable flip-flop

Details Scannable flip-flop Scannable flip-flop

1984-12-21

1987-05-26

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365201, 371 25, 307465, G11C 1140

Patent

active

046690611

ABSTRACT:
A digital circuit operable in a normal mode and in a test mode including memory elements which each operates as a static latch during the normal mode and operates as a dynamic master-slave flip-flop during the test mode. The digital circuit also includes combinational logic having a plurality of outputs, means operable in the normal mode to connect a combinational logic output to each of the inputs of the memory elements, and means operable in the test mode to connect outputs of memory elements to inputs of other memory elements so as to form a shift register to facilitate testing of complex digital circuits.

REFERENCES:
patent: 4390970 (1983-06-01), Kay
patent: 4540903 (1985-09-01), Cook et al.
King, "Dynamic LSSD Latch", IBM TDB, Dec. 1979, vol. 22, No. 7, p. 2618.
Moser, "LSSD Test Architecture", IBM Tech. Disc. Bull., vol. 24, No. 3, Aug. 1981, pp. 1666-1667.
Lo, "LSSD Implimented with DCVS Logic", IBM Tech. Disc. Bull., vol. 26, No. 11, Apr. 1984, pp. 5805-5810.

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