Scannable D flip-flop

Details Scannable D flip-flop Scannable D flip-flop

2011-03-29

2011-03-29

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S046000, C326S098000, C327S218000, C327S208000

Reexamination Certificate

active

07915925

ABSTRACT:
The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without compensating its testability. The embodiment of the present invention provides a scannable D flip-flop, comprising a source coupled logic, comprising a trigger circuit for reading a clock input; a scannable input circuit coupled to the trigger circuit having four NMOS transistors; a first feedback circuit for a first output; and a second feedback circuit for a second output; a latch circuit coupled to the source coupled logic; and an output buffer coupled to the latch circuit. Another embodiment of the present invention provides a scannable D flip-flop, comprising: a cascade dynamic logic, comprising: a first stage circuit; a second stage circuit coupled to the first stage circuit; a third stage circuit coupled to the second stage circuit; and a scannable input circuit coupled to the first stage circuit having four NMOS transistors for reading a data input and scannable inputs; a latch circuit coupled to the second stage circuit; and an output buffer coupled to the latch circuit.

REFERENCES:
patent: 7345519 (2008-03-01), Hirata
patent: 7596732 (2009-09-01), Branch et al.
N. Nedovic and V.G. Oklobdzija, “Dynamic Flip-Flop With Improved Power,” Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'00), 2000, pp. 323-326.
DeJan Markovic, Borivoje Nikolic and Robert W. Brodersen, “Analysis and Design of Low-Energy Flip-Flops,” ISPLED'01, Aug. 2001, pp. 52-55.
R. Ramanarayanan, N. Vijaykrishnon and M.J. Irwin, “Characterizing Dynamic and Leakage Power Behavior in Flip-Flops,” ASIC/SOC Conference, 2002. 15thAnnual IEEE International, 2002, pp. 433-437.
T. Hanyu, A. Mochizuki and M. Kameyama, “Multiple-Valued Dynamic Source-Coupled Logic,” Proc. 33rd. IEEE International Symposium on Multiple-Valued Logic, May 16-19, 2003, pp. 207-212.

Affiliated with

Also associated with

Rating

Scannable D flip-flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scannable D flip-flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scannable D flip-flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2663152