Scan test circuit and semiconductor integrated circuit device us

Details Scan test circuit and semiconductor integrated circuit device us Scan test circuit and semiconductor integrated circuit device us

1991-01-14

1992-07-14

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 371 223, G01R 1512, G06F 1100

Patent

active

051306476

ABSTRACT:
A data scan test circuit includes first through fourth latch circuits (L10 through L40). Data are latched in the third latch circuit (L40). A scan register consisting of the first, second and fourth latch circuits (L10, L20, L30) which become necessary when circuit blocks (CB1, CB2) are tested is made effective. Thus, unnecessary scan registers are put in the "through" state, thereby substantially reducing the number or scan paths in scan operation, and shortening the test time.

REFERENCES:
patent: 4780666 (1988-10-01), Sakashita et al.
patent: 4864579 (1989-09-01), Kishida et al.
patent: 4870345 (1989-09-01), Tomioka et al.
patent: 4995039 (1991-02-01), Sakashita et al.
patent: 5008618 (1991-04-01), Van Der Star
DasGupta et al., "An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceability", International Symposium on Fault-Tolerant Computing (Proceedings), IEEE, 1980.

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