Scan insertion testing of ASICs

Details Scan insertion testing of ASICs Scan insertion testing of ASICs

2006-01-17

2006-01-17

Wright, Norman M. (Department: 2134)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

C710S005000, C375S224000

Reexamination Certificate

active

06988207

ABSTRACT:
A circuit that uses a bi-directional buffer as follows: First a tri-state output buffer is connected to a functional clock and a bi-directional port is connected to a test clock. The bi-directional buffer is configured to receive control signals to selectively block and unblock the tri-state output port connected to the functional clock. In addition, the bi-directional port connected to a test clock is connected to the internal logic of the device. When the tri-state output buffer connected to the functional clock is blocked, the test clock transmits a clock signal to the internal logic of the device. When the tri-state output buffer connected to the functional clock is unblocked, the functional clock transmits a clock signal to the internal logic of the device.

REFERENCES:
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patent: 5227672 (1993-07-01), Sawtell
patent: 5329529 (1994-07-01), Murphy et al.
patent: 5982815 (1999-11-01), Ramirez
patent: 6208621 (2001-03-01), Ducaroir et al.
patent: 6804725 (2004-10-01), Whetsel
Technical Publication, “Designs with Multiple Clock Domains: Avoiding Clock Skew and Reducing Pattern Count Using DFTAdvisor™ and FastScan™”, Mentor Graphics Corporation, Mar., 2001.

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