Scan flip-flop and semiconductor integrated circuit device

Details Scan flip-flop and semiconductor integrated circuit device Scan flip-flop and semiconductor integrated circuit device

2002-09-04

2004-02-17

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S016000, C327S202000

Reexamination Certificate

active

06693460

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor integrated circuit device including a scan flip-flop and more particularly to a semiconductor integrated circuit device including a scan flip flop to be used in testing the semiconductor integrated circuit device.
BACKGROUND OF THE INVENTION
It has become difficult to test recent semiconductor integrated circuit devices (hereinafter referred to as “LSI's”) due to such LSI's having high integration and an increased number of input terminals. A technique for achieving testability of an LSI is by implementing a scan path method. A scan path method includes designing flip-flop circuits (scan flip-flops) that operate as shift registers. In this way, values stored in a scan flip-flop can be arbitrarily controlled and sampled by, for example, a tester at predetermined times by utilizing a shifting function.
To test an LSI by using a scan path method, the LSI is internally provided with a plurality of scan flip-flops. The scan flip-flops act as flip-flops and are used in a normal operation and in a scan test operation of the LSI. The input and output terminals of the scan flip-flops are serially connected (i.e., concatenated) to form a shift register circuit.
Each scan flip-flop is a circuit including a scan test operation function and a normal operation function. In a scan test operation function, the scan flip-flip acts as a flip-flop based on a data input from a scan-in signal SIN providing a test pattern signal to be latched based on a scan clock SC used as a test clock. In a normal operation function, a scan flip-flop acts as a normal flip-flop.
Scan flip-flops can be edge triggered. Scan flip-flops that operate off a rising clock edge are called a “positive F/F (flip-flop)” and scan flip-flops that operate off a falling clock edge are called a “negative F/F (flip-flop)”.
FIG. 4
is a circuit schematic diagram of a conventional scan flip-flop given the general reference character
400
. Conventional scan flip-flop
400
is a positive F/F and is hereinafter referred to as a conventional positive scan F/F
400
.
Referring now to
FIG. 4
, conventional positive scan flip-flop
400
includes a first master latching circuit
1
, a second master latching circuit
2
, a slave latching circuit
3
, and a clock circuit
4
. First master latching circuit
1
is used in a normal operation. Second master latching circuit
2
is used in a scan test operation. Slave latching circuit
3
is commonly used in the normal operation and the scan test operation. Clock circuit
4
generates signals for controlling the first master latching circuit
1
, second master latching circuit
2
, and the slave latching circuit
3
in accordance with a normal operation clock CLK, a first scan clock SC
1
, and a second scan clock SC
2
.
Clock circuit
4
includes inverters (IV
41
to IV
46
). Inverter INV
41
receives normal operation clock CLK as an input and provides an inverted normal operation clock at terminal AB. Inverter INV
42
has an input connected to terminal AB and provides a normal operation clock at terminal A. Inverter INV
43
receives first scan clock SC
1
as an input and provides an inverted first scan clock at terminal S
1
B. Inverter INV
44
has an input connected to terminal S
2
B and provides a first scan clock at terminal S
1
. Inverter INV
45
receives second scan clock SC
2
as an input and provides an inverted second scan clock at terminal S
2
B. Inverter INV
46
has an input connected to terminal S
2
B and provides a second scan clock at terminal S
2
.
First master latching circuit
1
includes transfer gates (TG
11
to TG
13
) and inverters (INV
11
and INV
12
). Transfer gate TG
11
is connected between an input terminal receiving input data D and an input of inverter INV
11
. Transfer gate TG
11
receives inverted normal operation clock from terminal AB and normal operation clock from terminal A as control signals. Transfer gate TG
12
is connected between an output of inverter INV
11
and an input of slave latching circuit
3
(at an input of inverter INV
31
). Transfer gate TG
12
receives inverted normal operation clock from terminal AB and normal operation clock from terminal A as control signals. Inverter INV
12
has an input connected to receive an output of inverter INV
11
. Transfer gate TG
13
is connected between an output of inverter INV
12
and an input of inverter INV
11
. Transfer gate TG
13
receives inverted normal operation clock from terminal AB and normal operation clock from terminal A as control signals. Transfer gate TG
11
is turned on when normal operation clock CLK has a low logic level and turned off when normal operation clock CLK has a high logic level. Transfer gates (TG
12
and TG
13
) are turned on when normal operation clock CLK has a high logic level and turned off when normal operation clock CLK has a low logic level.
Second master latching circuit
2
includes transfer gates (TG
21
to TG
23
) and inverters (INV
21
and INV
22
). Transfer gate TG
21
is connected between an input terminal receiving a scan-in signal SIN and an input of inverter INV
21
. Transfer gate TG
21
receives inverted first scan clock from terminal S
1
B and first scan clock from terminal S
1
as control signals. Transfer gate TG
22
is connected between an input of inverter INV
21
and an output terminal providing output signal Q. Transfer gate TG
22
receives inverted second scan clock from terminal S
2
B and second scan clock from terminal S
2
as control signals. Inverter INV
21
has an output connected to an input of inverter INV
22
. Transfer gate TG
23
is connected between an output of inverter INV
22
and an input of inverter INV
21
. Transfer gate TG
22
receives inverted first scan clock from terminal S
1
B and first scan clock from terminal S
1
as control signals. Transfer gate TG
21
is turned on when first scan clock SC
1
has a high logic level and turned off when first scan clock SC
1
has a low logic level. Transfer gate TG
22
is turned on when second scan clock SC
2
has a high logic level and turned off when second scan clock SC
2
has a low logic level. Transfer gate TG
23
is turned on when first scan clock SC
1
has a low logic level and turned off when first scan clock SC
1
has a high logic level.
Slave latching circuit
3
includes transfer gates (TG
31
and TG
32
) and inverters (INV
31
and INV
32
). Inverter INV
31
has an input connected to receive an output from first master latching circuit
1
. Transfer gate TG
31
is connected between an output of inverter INV
31
and a terminal providing output signal Q. Inverter INV
32
has an input connected to receive output signal Q. Transfer gate TG
32
is connected between an output of inverter INV
32
and an input of inverter INV
31
. Transfer gate TG
31
is turned on when second scan clock SC
2
has a low logic level and turned off when second scan clock SC
2
has a high logic level. Transfer gate TG
32
is turned on when normal operation clock CLK has a low logic level and turned off when normal operation clock CLK has a high logic level.
Slave latching circuit
3
has an output (i.e., the output of transfer gate TG
31
) commonly connected with an output (i.e., the output of transfer gate TG
22
) of second master latching circuit
2
. In this way, data Q is provided from transfer gate TG
22
in synchronism with a rising edge of second scan clock SC
2
when operating in a scan mode of operation.
The operation of conventional positive scan flip-flop
400
will now be explained.
First a normal operation will be explained.
In a normal operation of conventional positive scan flip-flop
400
, first scan clock SC
1
is at a “0” (logic low) and second scan clock SC
2
is held at a “0” (logic low). Thus, transfer gates (TG
21
and TG
22
) in second master latching circuit
2
are both turned off. Transfer gate TG
23
in second master latching circuit
2
is turned on. Transfer gate TG
31
in slave latching circuit
3
is turned on.
Then, when normal operation clock CLK falls (becomes logic low), transfer gate TG
11
in fir

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