Scan compatible 3-state bus control

Details Scan compatible 3-state bus control Scan compatible 3-state bus control

1995-11-01

1997-07-15

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 16, 326 56, H03K 190175

Patent

active

056487339

ABSTRACT:
Bus control circuitry for enabling/disabling the drivers of a bus in an integrated circuit is presented. The bus control circuitry has master control signal logic blocks and output enable blocks. The bus control circuitry enables one and only one bus driver set at a time to avoid bus contention. Furthermore, the bus driver circuits are enabled and disabled with precise timing to avoid even momentary bus contention. Finally, the bus, driver circuits and control circuitry may be tested with serial scanning.

REFERENCES:
patent: 4587445 (1986-05-01), Kanuma
patent: 4800486 (1989-01-01), Horst et al.
patent: 4857773 (1989-08-01), Takata et al.
patent: 5118970 (1992-06-01), Olson et al.
patent: 5394034 (1995-02-01), Becker et al.
Wakerly, John F.; "Digital Design: Principles and Practices"; copyright 1989 by John F. Wakerly; p. 274.

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