Scan chain element and associated method

Details Scan chain element and associated method Scan chain element and associated method

2006-05-02

2006-05-02

Dildine, R. Stephen (Department: 2133)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C714S726000, C327S202000

Reexamination Certificate

active

07038494

ABSTRACT:
A scan chain element in an integrated circuit, the scan chain element including; a first latch connected to accept test data as an input, a second latch connected to accept the output of the first latch as an input, control logic for accepting a clock signal and a hold signal, the scan chain element being operable in a first mode such that the control logic is configured to supply the clock signal to the first latch and subsequently, in response to the hold signal, to supply the clock signal to the second latch to latch the data from the output of the first latch.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 6148425 (2000-11-01), Bhawmik et al.
patent: 2005/0005214 (2005-01-01), Ueda
Sheth, A.M.; Savir, J.; Single-clock, single-latch, scan design; Instrumentation and Measurement, IEEE Transactions on; vol.: 52 Issue: 5 Oct. 2003; pp.: 1455-1457.

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