Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-05-15
2009-11-03
Baderman, Scott T (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
07613951
ABSTRACT:
The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented changing state when new information is generated. The trace logic, whose clock is free running, detects the change in state in the valid signal. It then processes the trace information presented to it, exporting this information to a trace recorder. When transmission of this information has created sufficient space to accept a new frame of trace information, the empty signal is generated. This causes the clock generation logic to issue another clock to the system logic.
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Baderman Scott T
Brady III Wade J.
Leibovich Yair
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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