Scaled stack-gate non-volatile semiconductor memory device

Details Scaled stack-gate non-volatile semiconductor memory device Scaled stack-gate non-volatile semiconductor memory device

2001-10-09

2002-10-15

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S321000, C257S322000

Reexamination Certificate

active

06465837

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a stack-gate non-volatile semiconductor device and more particularly to scaled stack-gate non-volatile semiconductor memory devices having a tapered floating-gate structure for high-density mass storage applications.
DESCRIPTION OF RELATED ART
A non-volatile semiconductor memory device is known to store charges in an isolated gate (known as a floating gate ) by means of either Fowler-Nordheim tunneling or hot-electron injection of electrons through a thin tunneling-dielectric layer from a semiconductor substrate and to remove or erase charges stored in an isolated gate by means of Fowler-Nordheim tunneling through a thin tunneling-dielectric layer to a semiconductor substrate or a control gate. Basically, the cell size of a non-volatile semiconductor memory device must be scaled down for high-density mass storage applications and the cell structure must be developed toward low voltage, low current and high-speed operation with high endurance and high retention.
In general, based on the cell structure the non-volatile semiconductor memory devices of the prior art can be divided into two categories: a stack-gate structure and a split-gate structure. The stack-gate structure is known to be a one-transistor cell, in which the gate length of a cell can be defined by using the minimum-feature-size of technology used. However, the split-gate structure including a floating-gate and a select gate is known to be a 1.5-transistor cell. Therefore, the stack-gate structure is more suitable for high-density mass storage applications than the split-gate structure.
FIG. 1
shows a cross-sectional view of a stack-gate non-volatile semiconductor memory device of the prior art having an asymmetrical source/drain diffusion region, in which a stack-gate structure including a masking dielectric layer
105
, a control-gate layer (CG)
104
, an intergate dielectric layer
103
, and a floating-gate layer (FG)
102
is formed vertically over a thin tunneling-oxide layer
101
by anisotropic dry etching. A deeper source diffusion region
106
a
is formed by implanting a moderate dose of doping impurities into a semiconductor substrate
100
using a non-critical masking photoresist step and the phosphorous ions are frequently used. The shallow source and drain diffusion regions
107
a
,
107
b
are formed by implanting a high dose of doping impurities into a semiconductor substrate
100
in a self-aligned manner and the arsenic ions are frequently used. The dielectric spacers
108
a
are formed over the sidewalls of the stack-gate structure for forming the self-aligned contacts over the shallow source and drain diffusion regions
107
a
,
107
b
. The particular source doping structure shown in
FIG. 1
is suitable for a stack-gate non-volatile semiconductor device being operated by channel hot-electron injection (CHEI) of hot electron into the floating gate
102
for programming and by Fowler-Nordheim tunneling of stored electrons in the floating gate
102
into the double-diffused source structure for erasing. The double-diffused source structure is used not only to eliminate the band-to-band tunneling effect for a positive source voltage applied for erasing but also to offer a larger overlapping area for erasing. It is clearly visualized that the deeper source diffusion region in the double-diffused source structure becomes an obstacle as the stack-gate length is further scaled down.
FIG. 2
shows a cross-sectional view of a stack-gate non-volatile semiconductor memory device of the prior art having a symmetrical source/drain diffusion region, in which the deeper source diffusion region
106
a
in
FIG. 1
is removed. This particular doping structure is suitable for a stack-gate non-volatile semiconductor memory device being operated by Fowler-Nordheim tunneling of electrons between the floating-gate
102
and the semiconductor substrate
100
. However, as the stack-gate length and width are scaled down, the effective tunneling area for programming/erasing is drastically reduced, resulting in higher programming/erasing time.
According to the above description, the stack-gate non-volatile semiconductor memory device of the prior arts is difficult to be scaled further. It is, therefore, an objective of the present invention to offer a stack-gate structure having a tapered floating-gate structure for a scaled stack-gate non-volatile semiconductor device.
SUMMARY OF THE INVENTION
The present invention discloses scaled stack-gate non-volatile semiconductor memory devices having a tapered floating-gate structure for high-density mass storage applications. A stack-gate structure of the present invention including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer on a thin tunneling-dielectric layer is formed on a semiconductor substrate having an active region isolated by field oxides and is oxidized to form a first thin poly-oxide layer over the sidewalls of the control-gate layer, a second thin poly-oxide layer over the sloped sidewalls of the tapered floating-gate layer, and a thicker oxide layer formed over each side portion of the active region having a graded-oxide layer formed near two gate edges. Different source and drain doping structures are formed in a self-aligned manner in each side portion of the active region and a dielectric spacer is formed over the sidewalls of the stack-gate structure for forming a self-aligned source/drain contact for a scaled non-volatile semiconductor memory device.
The first embodiment of the present invention is a scaled stack-gate non-volatile semiconductor memory device having a tapered floating-gate structure with a deeper double diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region, which offers a larger overlapping area between the tapered floating-gate layer and a deeper double-diffused source region for erasing by tunneling stored electrons in the tapered floating-gate layer into the deeper double-diffused source region without inducing the band-to-band tunneling effects and offers a longer effective channel length to alleviate the punch-through effect for programming using channel hot-electron injection.
The second embodiment of the present invention is a scaled stack-gate non-volatile semiconductor memory device having a tapered floating-gate structure with a deeper double-diffused source/drain region having a graded doping profile formed near two gate edges, which offers a larger overlapping area between the tapered floating-gate layer and a deeper double-diffused source/drain region for programming and erasing by tunneling electrons between the tapered floating-gate layer and a deeper double-diffused source/drain region without inducing the band-to-band tunneling effects and with alleviating the punch-through effects.
The third embodiment of the present invention is a scaled stack-gate non-volatile semiconductor memory device having a tapered floating-gate structure with a shallower double-diffused source/drain region having a graded doping profile formed near two gate edges, which offers a larger channel area for programming and erasing by tunneling electrons between the tapered floating-gate layer and the semiconductor substrate without inducing the band-to-band tunneling effects and with alleviating the punch-through effects.


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patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 6069382 (2000-05-01), Rahim
patent: 6252271 (2001-06-01), Gambino et al.
patent: 6323086 (2001-11-01), Hsu et al.
patent: 2001/0001212 (2001-05-01), Gambino et al.
patent: 2001/0014501 (2001-08-01), Hsu et al.

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