Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-09
2002-10-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S317000, C257S322000, C257S324000, C257S318000, C438S020000, C438S211000, C438S258000, C438S261000, C438S264000, C438S259000, C365S185050, C365S185330, C365S185240, C365S185140, C365S185300, C365S185270
Reexamination Certificate
active
06462372
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a stack-gate flash memory device and more particularly to a scaled stack-gate flash memory device having an integrated source/drain landing island acted as a field-emission cathode/anode for erasing and programming without involving the channel region.
DESCRIPTION OF RELATED ART
The stack-gate structure is known to be a one-transistor structure for a flash memory device, in which the gate length can be defined by using the minimum-feature-size of technology used. Basically, a stack-gate flash memory device can be programmed by either channel hot-electron injection (CHEI) or Fowler-Nordheim tunneling, depending on the source and drain structure formed in a semiconductor substrate.
FIG. 1
shows a typical stack-gate structure used in the prior art, in which a double-diffused source structure is formed to offer a larger overlapping area for tunneling stored electrons from the floating-gate (FG) layer
102
a
to the deeper double-diffused source region
106
a
without inducing the band-to-band tunneling effects, and a shallow heavily-doped drain diffusion region
110
a
is used to tailor a peak electric field near the drain edge for channel hot-electron generation. From
FIG. 1
, it is clearly seen that the double-diffused source structure becomes an obstacle as the gate length is further scaled down because the punch-through effect becomes an important issue for device design. Moreover, the most of the drain current is wasted during programming and the programming time becomes a major concern for high-density mass storage applications.
FIG. 2
shows a much simpler stack-gate structure, in which a deeper source diffusion region
106
a
in a double-diffused source structure shown in
FIG. 1
is deleted and a masking photoresist step for forming the deeper source diffusion region
106
a
isn't required. This structure is operated by tunneling electrons between the floating-gate layer
102
a
and the semiconductor substrate
100
for programming and erasing. It is clearly seen that the channel area for programming and erasing becomes smaller as the gate length is scaled down. As a consequence, the programming and erasing time will be longer as the gate-length becomes shorter.
Based on the above description, the stack-gate structure cann't be easily scaled down if the programming or erasing involves the channel region. It is, therefore, a major objective of the present invention to offer a stack-gate structure with an integrated source and drain landing island being acted as a field-emission cathode and anode for programming and erasing of a scaled stack-gate flash memory device without involving the channel region.
SUMMARY OF THE INVENTION
A stack-gate structure having a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a floating-gate layer formed on a gate-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized to form a first dielectric layer over the sidewalls of the control-gate layer, a second dielectric layer over the sidewalls of the floating-gate layer, and a thicker oxide layer formed over each side portion of the active region having a graded-oxide layer formed near two gate edges. The floating-gate layer can be etched to have a taper angle being equal to or smaller than 90 degrees. A source/drain diffusion region is formed over each side portion of the active region. An integrated source/drain landing island including a portion formed on a source/drain diffusion region for contact and an extended portion formed over the second dielectric layer and on the graded-oxide layer is acted as a field-emission cathode/anode with respect to the sidewalls of the floating-gate layer and is oxidized. A dielectric spacer is formed over the sidewalls of the masking dielectric layer, the control-gate layer, and the intergate dielectric layer for self-aligned silicidation of the integrated source/drain landing island.
The scaled stack-gate flash memory device as described can be operated for erasing by tunneling electrons from the integrated source landing island into the floating-gate layer through two tunneling paths: one is from the extended portion of the integrated source landing island through the second dielectric layer; the other is from the overlapped source diffusion region through the gate-dielectric layer, and for programming by tunneling stored electrons from the floating-gate layer into the integrated drain landing island through two tunneling paths: one is from the floating-gate layer to the extended portion of the integrated drain landing island through the second dielectric layer; the other is from the floating-gate layer to the overlapped drain diffusion region through the gate-dielectric layer. As electrons are stored in the floating-gate layer for erasing, the threshold voltage of a scaled stack-gate flash memory device is high; as stored electrons are removed from the floating-gate layer for programming, the threshold voltage of a scaled stack-gate flash memory device is low.
The tunneling path from the source diffusion region to the floating-gate layer and the tunneling path from the floating-gate layer to the drain diffusion region can be prohibited if the thickness of the gate-dielectric layer is made to be thicker or the same as those used in peripheral devices. A scaled stack-gate flash memory device can be operated for programming and erasing with one tunneling path.
Therefore, the scaled stack-gate flash memory device of the present invention can be programmed and erased without involving the channel region and the gate length can be easily scaled down further for highdensity mass storage applications.
REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5688705 (1997-11-01), Bergemount
patent: 6008089 (1999-12-01), Hong
patent: 6020257 (2000-02-01), Leedy
patent: 6038171 (2000-03-01), McElheny
patent: 6087695 (2000-07-01), Chen
patent: 6218689 (2001-04-01), Change et al.
patent: 6225164 (2001-05-01), Lim
patent: 2001/0008290 (2001-07-01), Lim
patent: 2001/0019151 (2001-09-01), Caywood
Seiichi Aritome, “Advanced Flash Memory Technology an Trends for File Storage Application”, IEDM, pp. 763-766.
J. D. et al., Choi et al., A 0.15 um NAND Flash Technology with 0.11 um2 Cell Size for 1 Gbit Flash Memory; IEDM, pp. 767-770.
S. Wolf and R. N. Tauber, “Silicon Processing for the VlSi Era,”, vol. 1-Process Technology, Lattice Press 1986, pp. 555-558 in Chapter 16.
Manufacturing Methods, pp. 641-650.
Erdem Fazli
Flynn Nathan J.
Powell Goldstein Frazer & Murphy LLP
Silicon-Based Technology Corp.
LandOfFree
Scaled stack-gate flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scaled stack-gate flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scaled stack-gate flash memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2922556