Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-01-29
2004-03-23
Phung, Anh (Department: 2652)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06711053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory cells, array structures for memory cells, and methods for writing and reading the memory cells. More particularly, this invention relates to magnetic random access memory (MRAM) cells, array structures for MRAM cells, and methods for writing and reading MRAM cells.
2. Description of Related Art
Magneto-electronic memories are emerging as important memory technologies. Presently, there are three types of magnetic memory devices that are grouped according to the physics of their operation. These categories are a hybrid ferromagnetic semiconductor structure, a metal spin transistor or spin valve, and a tunnel magnetic junction. Writing to memories of each of the devices is essentially the same in that the direction of a magnetic field determines the state of the digital data stored in a memory cell. Reading of each of the devices is different for each of the devices. The ferromagnetic semiconductor device essentially employs a Hall Effect to determine the state of the digital data stored in the memory cell. The metal spin transistor and the magnetic tunnel junction each employ a change in magneto-resistance to determine a state of the digital data stored in the memory cell. In a metal spin transistor, the relative resistance difference is on the order of from 6% to 8%. The discrimination of the state of the digital data is difficult with the metal spin transistor. However, the magnetic tunnel junction has a resistance difference on the order of 12%.
U.S. Pat. No. 6,269,018 (Monsma, et al.), U.S. Pat. No. 5,978,257 (Zhu, et al.) and U.S. Pat. No. 5,699,293 (Tehrani, et al.) illustrate the structure of magnetic tunnel junction devices as used for memory cells. The magnetic tunnel junction is a tri-layer structure in which two ferromagnetic layers are separated by a nonmagnetic tunnel barrier. One of the ferromagnetic layers has a fixed magnetic field and the other ferromagnetic layer is connected to have its magnetic orientation modified dependent upon the current flowing through the layer. If the magnetic fields of the two ferromagnetic layers are parallel, the magnetic junction has a lower resistance than if the fields are anti-parallel. This difference in resistance allows the sensing of the digital data being stored in the magnetic tunnel junction.
Tehrani, et al. demonstrates a method of operating a random access memory device constructed from a MRAM device. The MRAM device has a group of pairs of memory cells, a column decoder, a row decoder, and a comparator. The pair of memory cells is designated by column decoder and row decoder (32) in response to a memory address. Complementary bits (“0” and “1”) are stored in the pair of memory cells. When the state in the pair of memory cell is read, both bits in the pair of memory cells are compared to produce an output at one read cycle time to a bit line.
Zhu, et al. describes a MRAM cell having two magnetic layers with an insulating layer sandwiched between. Conductive layers are connected to each of the magnetic layers. A word line is adjacent to or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the two conductive layers sufficient to switch vectors in the two magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the two conductive layers, and measuring a resistance across the cell.
Monsma, et al. illustrates a MRAM using current through MTJ write mechanism. Each memory cell of the memory includes a magnetic tunnel junction device having two free ferromagnetic layers and a highly conductive layer formed between the first ferromagnetic layer and the second ferromagnetic layer of the magnetic tunnel junction device. A write current through each selected memory cell flows into the highly conductive layer and along at least a portion of the highly conductive layer. A self-field associated with the write current changes a first predetermined magnetization of the first and second ferromagnetic layers to a second predetermined magnetization. A second embodiment of the memory cell includes a magnetic tunnel junction device having a free ferromagnetic layer, a pinned ferromagnetic layer, and a tunneling barrier layer formed between the free and pinned ferromagnetic layers. The free ferromagnetic layer has a magnetization in a form of a vortex. The pinned ferromagnetic layer has substantially the same shape as the shape of the free ferromagnetic layer and a magnetization in a form of a vortex. A write current flows through the memory cell and producing a self-field that changes a magnetic vortex state of the free ferromagnetic layer from one orientation to a second orientation.
U.S. Pat. No. 6,331,943 (Naji, et al.) describes a magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns. Each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.
SUMMARY OF THE INVENTION
An object of this invention is to provide a MRAM cell for the storage, retention, and recovery of digital data.
Another object of this invention is to provide a MRAM array for the storage, retention, and recovery of digital data.
Further, another object of this invention is to provide a method for operating a MRAM cell.
To accomplish at least one of these objects and other objects, a MRAM array has groupings of MRAM cells. The MRAM cells are interconnected by word control lines to provide a control signal for accessing the memory structure.
The grouping of MRAM cells are organized into a memory structure, each memory structure has at least one local program control line to provide a program current for writing a digital data bit within the memory structure. The MRAM cells of the memory structure are arranged in rows and columns. The each column of MRAM cells is connected to one local program control line and each row of MRAM cells is connected to a word control line. Each MRAM cell is comprised of a magnetic tunnel junction and a primary switching device. One terminal of the primary switching device is connected to one of the primary program control lines to provide the write current to magnetic tunnel junction. A control terminal of the primary switching device is connected to one of the word control lines. The word control line selectively activates the primary switching device to permit the write current to flow to the magnetic tunnel junction when the word control line is set to a select state. When the word control line is set to the deselect state the write current is prevented from flowing to the magnetic tunnel junction.
The write current flows through a pinned ferromagnetic layer of the magnetic tunnel junction to store the state of the digital data to the MRAM cell. The direction of the write current flow determining a magnetic field of the pinned ferromagnetic layer. The current flow being between the primary program control line and local program control line.
In a first embodiment, the a second terminal of the primary switching device is connected to one side of the pinned ferromagnetic layer such that
Ackerman Stephen B.
Knowles Billy
Phung Anh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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