Scaleable bandwidth interconnect for simultaneous transfer...

Details Scaleable bandwidth interconnect for simultaneous transfer... Scaleable bandwidth interconnect for simultaneous transfer...

1999-12-27

2003-06-24

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S305000, C709S249000

Reexamination Certificate

active

06584521

ABSTRACT:

FIELD
The present invention relates to a scalable bandwidth interconnect bus that provides a multipoint-to-multipoint interconnection between communications devices supporting a large number of individual links for use as a high channel density interconnect with optional cross connect capability. The scalable bandwidth interconnect bus supports a synchronous mode of operation as well as an asynchronous mode of operation employing flexible timing mastership.
BACKGROUND
Typically, an optical fiber, twisted pair electrical or coaxial cable is used for an electrical transmission facility. Such a facility is coupled to a physical medium dependent sub layer (PMD sub layer) which is the lowest sub layer of the two sub layers of the physical layer. The physical layer is the lowest level layer function of the layer functions in the Broadband Integrated Services Digital Network model. The physical layer is responsible for typical physical layer functions, such as bit transfer/reception and bit synchronization. There is a need for interface devices that interconnect physical layer devices including channelized framers with link layer devices of widely varying channel densities and payload types.
SUMMARY OF THE INVENTION
According to the invention there is provided a scalable bandwidth interconnect (SBI) for interconnection of physical layer devices with link layer devices which includes an ADD BUS interface operative to receive data from one or more link layer devices and direct it to one or more physical layer devices and a DROP BUS interface operative to receive data from one or more physical layer devices and direct it to one or more link layer devices. The utilization of buses to access each of the physical layer devices and the link layer devices permits interfacing between a large number of physical layer devices and a large number of link layer devices. Each physical layer device or link layer device may itself handle many links.
The data structures of the SBI may be floating to permit compensation between clock differences on the physical layer devices, the SBI and the link layer devices.
On a per link basis the timing of the link recovered by the physical layer device may be transferred to the DROP BUS interface. On a per link basis the timing on the ADD BUS interface may be transferred from one of the link layer devices or one of the physical layer devices.
Data structures of the SBI may be operative to transfer ABCD signaling bits, alarm indications, 8 kHz timing, and/or per link clock reconstruction information across said SBI.
Links in the form of T1, E1, DS3, and E3 signals may be multiplexed onto and demultiplexed from the SBI bus.
The SBI bus provides an association or mapping function for links between large numbers of physical layer links and link layer links.
The interconnect may have a time division multiplexed bus which has a SONET/SDH virtual tributary structure to carry T1 links, E1 links and Transparent Virtual Tributaries (TVTs).
The location of T1/E1/DS3/E3/TVT1.5/TVT2 channels may be adjusted using floating tributaries to compensate for frequency deviations.
Each frame may have three synchronous payload envelopes with each envelope carrying one of T1, E1, TVT1.5, TVT2, DS3 and E3 tributaries in an SDH STM-1 like format.
The SBI may have payload indicator signals to control position and timing of the floating data structures. The timing information may be obtained by one of the physical layer devices from an arrival rate of data across said SBI when one of the link layer devices is timing master.
A justification request signal may be sent by one of the PHY devices which is timing master to one of the link layer devices to signal the link layer device to speed up or slow down.
The link layer devices may have high density physical layer framers.
The SBI may be scaleable by increasing the bus clock rate in multiples of 2 or, alternatively, by increasing the bus width in multiples of two.


REFERENCES:
patent: 6101567 (2000-08-01), Kim et al.
patent: 6247083 (2001-06-01), Hake et al.
patent: 6366630 (2002-04-01), Okuyama
COMBUS—A Backplane Bus and Package for SONET Applications, IEEE P1396.A/D6.0 (First Draft), Nov. 30, 1990.
American National Standard for Telecommunications—Synchronous Optical Network (SONET)—Payload Mappings, ANSI T1.105.02-1995.
GO-MVIP, H-MVIP standard, Release 1.1a, 1997.
American National Standard for Telecommunications—Synchronous Optical Network (SONET)—Basic Description Including Multiplex Structure, Rates, and Formats, ANSI T1.105-1995.
ITU-T, Series G: Transmission Systems and Media, Network Node Interface for the Synchronous Digital Hierarchy (SDH), G.707, Mar., 1996.

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