Scalable unified memory architecture

Details Scalable unified memory architecture Scalable unified memory architecture

2005-03-08

2005-03-08

Bella, Matthew C. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Shared memory

C345S543000, C345S544000

Reexamination Certificate

active

06864896

ABSTRACT:
A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

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patent: 5867180 (1999-02-01), Katayama et al.
patent: 6104417 (2000-08-01), Nielsen et al.
patent: 6208273 (2001-03-01), Dye et al.
patent: 6690726 (2004-02-01), Yavits et al.

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