Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-30
2003-04-22
Nô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S321000
Reexamination Certificate
active
06552386
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a split-gate flash memory cell and its flash memory array and, more particularly, to a scalable split-gate flash memory cell having a controllable tip-cathode floating-gate structure and its contactless flash memory arrays.
DESCRIPTION OF THE RELATED ART
The split-gate flash memory cell structure having a select-gate region and a gate-stack region offers in general a larger cell size as compared to that of a stack-gate flash memory cell structure and is usually configured to be a NOR-type array. Two typical split-gate flash memory cell structures are shown in FIG.
1
A and FIG.
1
B.
FIG. 1A
shows a split-gate flash memory cell structure having a floating-gate layer
11
formed by a local oxidation of silicon (LOCOS) technique, in which the floating-gate length is defined in general to be larger than a minimum-feature-size (F) of technology used due to the bird's beak formation at two gate edges; a control-gate layer
15
is formed over a part of a LOCOS-oxide layer
12
and a thicker select-gate oxide layer
14
; a poly-oxide layer
13
is formed over a sidewall of the floating-gate layer
11
; a source diffusion region
16
and a drain diffusion region
17
are formed in a semiconductor substrate
100
in a self-aligned manner; and a thin gate-dielectric layer
10
is formed under the floating-gate layer
11
. The split-gate flash memory cell structure shown in
FIG. 1A
is programmed by mid-channel hot-election injection, the programming efficiency is higher and the programming power is lower as compared to the channel hot-electron injection used by the stack-gate flash memory cell structure. Moreover, the over-erase problem of the split-gate flash memory cell structure can he prevented due to a high threshold-voltage of the select-gate transistor in the select-gate region, so the control logic circuits for erasing and verification can be simplified. However, there are several drawbacks for FIG.
1
A: the cell size is larger due to a non-self-aligned control-gate structure; the gate length can't be easily scaled due to the misalignment of the control-gate layer
15
with respect to the floating-gate layer
11
; the coupling ratio is low and higher applied control-gate voltage is required for erasing; the field-emission tip of the floating-gate layer
11
is difficult to be controlled due to the weak masking ability of the bird's beak of the LOCOS oxide layer
12
; and a high-temperature oxidation process is required to form a LOCOS-oxide layer
12
with an appreciate tip.
FIG. 1B
shows another split-gate flash memory cell structure, in which a floating-gate layer
21
is defined by a minimum-feature-size (F) of technology used; a thin tunneling-oxide layer
20
is formed under the floating-gate layer
21
; a select-gate oxide layer
22
is formed over a semiconductor substrate of the select-gate region and an exposed floating-gate layer
21
; a control-gate layer
23
is formed above a portion of the floating-gate layer
21
and the select-gate region; and a source diffusion region
24
and a double-diffused drain structure
25
/
26
are formed in a semiconductor substrate
100
. From
FIG. 1B
, it is clearly visualized that similar drawbacks are appeared except that the erasing site is located at the thin tunneling-oxide layer
20
between the floating-gate layer
21
and the double-diffused drain structure
25
/
26
. Apparently, the double-diffused drain structure
25
/
26
is mainly used to eliminate the band-to-band tunneling effect and becomes an obstacle for further scaling.
It is, therefore, an objective of the present invention to provide a scalable split-gate flash memory cell structure with a scalable cell size being equal to or smaller than 4F
2
.
It is another objective of the present invention to provide a controllable tip-cathode structure for the scalable split-gate flash memory cell with a higher erasing efficiency.
It is a further objective of the present invention to provide a manufacturing method with less critical masking steps.
It is yet another objective of the present invention to provide two contactless array architectures for high-speed operations with less power consumption.
SUMMARY OF THE INVENTION
A scalable split-gate flash memory cell structure of the present invention is fabricated on a semiconductor substrate of a first conductivity type with an active region being formed between two shallow-trench-isolation (STI) regions and comprises a common-source region, a scalable split-gate region, and a scalable common-drain region, wherein the scalable split-gate region is formed between the common-source region and the scalable common-drain region. The common-source region comprises a common-source diffusion region of a second conductivity type being formed in the active region, a first sidewall dielectric spacer being formed over an outer sidewall of the scalable split-gate region and on a portion of a flat surface being formed by a tunneling-dielectric layer in the active region and two fourth raised field-oxide layers in the two STI regions, a common-source conductive bus-line being formed over a first flat bed outside of the first sidewall dielectric spacer, and a first planarized thick-oxide layer being formed over the common-source conductive bus-line, wherein the common-source diffusion region comprises a shallow heavily-doped common-source diffusion region being formed within a lightly-doped common-source diffusion region and the first flat bed comprises the shallow heavily-doped common-source diffusion in the active region and two fifth raised field-oxide layers in the two STI regions. The scalable split-gate region being defined by a third sidewall dielectric spacer formed over an outer sidewall of the common-source region comprises a floating-gate region being defined by a second sidewall dielectric spacer formed over the outer sidewall of the common-source region and a select-gate region being formed outside of the floating-gate region, wherein a floating-gate layer over a thin tunneling-dielectric layer is formed over the semiconductor substrate in the active region of the floating-gate region and a portion of a control-gate conductive layer over a gate-dielectric layer is formed over an implant region of the first conductivity type in the active region of the select-gate region. The implant region comprises a shallow implant region for threshold-voltage adjustment of the select-gate transistor and a deep implant region for forming a punch-through stop. The floating-gate layer comprises a tip-cathode line being formed between a first thermal poly-oxide layer formed over an outer sidewall of the floating-gate layer near the select-gate region and a refilled-oxide layer formed over an upper corner portion of the floating-gate layer near the common-source region, and a second thermal poly-oxide layer being formed over the tip-cathode line as a tunneling-dielectric layer. A control-gate conductive layer capped with a capping control-gate conductive layer is formed over the floating-gate region and the select-gate region in the scalable split-gate region to act as a conductive word-line for forming a first-type scalable split-gate flash memory cell of the present invention, wherein a planarized capping-oxide layer is formed over the capping control-gate conductive layer. A metal word-line integrated with a planarized control-gate conductive island over a control-gate conductive island is patterned to be aligned above the active region for forming a second-type scalable split-gate flash memory cell of the present invention, wherein the control-gate conductive island is formed over the floating-gate layer in the floating-gate region and the gate-dielectric layer in the select-gate region. The scalable common-drain region comprises a common-drain diffusion region of the second conductivity type and a fourth sidewall dielectric spacer being formed over another sidewall of the scalable split-gate region and on a portion of second flat bed, wherein the common-drain diffusion reg
Nô Ngân V.
Pro-Techtor Inter-national Services
Silicon-Based Technology Corp.
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