Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2006-07-03
2009-08-04
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S130000, C711S141000, C711S147000
Reexamination Certificate
active
07571288
ABSTRACT:
Object rundown protection that scales with the number of processors in a shared-memory computer system is disclosed. Prior to object rundown, a cache-aware reference count data structure is used to prevent cache-pinging that would otherwise result from data sharing across processors in a multiprocessor computer system. In this data structure, a counter of positive references and negative dereferences, aligned on a particular cache line, is maintained for each processor. When an object is to be destroyed, a rundown wait process is begun, during which new references on the object are prohibited, and the total number of outstanding references is added to an on-stack global counter. Destruction is delayed until the global reference count is reduced to zero. In an implementation on non-uniform memory access multiprocessor machines, each processor's reference count is additionally allocated in a region of main memory that is physically close to that processor.
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Christiansen Neal R.
Clift Neill
Pudipeddi Ravisankar
Merchant & Gould P.C.
Microsoft Corporation
Verbrugge Kevin
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