Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-03-01
2011-03-01
Blum, David S (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257SE29309
Reexamination Certificate
active
07898022
ABSTRACT:
A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO2and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.
REFERENCES:
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 6855979 (2005-02-01), Sadd et al.
patent: 6885060 (2005-04-01), Nomoto et al.
patent: 6887758 (2005-05-01), Chindalore et al.
patent: 6888200 (2005-05-01), Bhattacharyya
C. Gerardi et al., Fast and Low Voltage Program / Erase in Nanocrystal Memories: Impact of Control Dielectric Optimization, Non Volatile Semiconductor Memory Workshop 2004, pp. 71, 2004.
C.M. Compagnoni et al., Study of Data Retention for Nanocrystal Flash Memories, IEEE 41stAnnual Intl. Reliability Physics Symposium, Dallas, Texas, 2003, pp. 506-512.
R. Ohba et al., Impact of Stoichiometry Control in Double Junction Memory on Future Sealing, IEDM, 2004, pp. 897-900.
C. Monzio Compagnoni et al., Program/Erase Dynamics and Channel Conduction in Nanocrystal Memories, IEDM, 2003, pp. 550-553.
Y.Q. Wang et al., Formation of Ge Nanocrystals in HfAIO High-k Dielectric and Application in Memory Device, vol. 84, No. 26, Jun. 2004, pp. 5407-5409.
D. Zhao et al., Simulation of Hetero-nanocrystal Floating Gate Flash Memory, IEDM, 2004.
R. Gupta et al., Formation of SiGe Nanocrystals in Hf02Using In-Situ Chemical Vapor Deposition for Memory Application, Applied Physics Letters, vol. 84, No. 21, May 2004, pp. 4331-4333.
S. Lombardo et al., Distribution of the Threshold Voltage Window in Nanocrystal Memories with Si Dots Formed by Chemical Vapor Deposition: Effect of Partial Self-Ordering, NVSMW, 2004, pp. 69-70.
M. Kanoun et al., Electrical Study of Ge-Nanocrystal-Based Metal-Oxide-Semiconductor Structures for P-Type Nonvolatile Memory Applications, Applied Physics Letters, vol. 84, No. 25, Jun. 2004, pp. 5079-5081.
M. Koyanagi et al., Metal Nano-Dot Memory for High Density Non-Volatile Memory Application, IEEE SNVMW, 2004, pp. 0/7803-8511-X/04.
P. Dimitrakis et al., Silicon Nanocrystal Memory Devices Obtained by Ultra-Law-Energy Ion-Beam Synthesis, International Solid State Electronics, 48, 2004, pp. 1511-1517.
Blum David S
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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