Scalable modular architecture for parity calculation

Details Scalable modular architecture for parity calculation Scalable modular architecture for parity calculation

2006-02-14

2006-02-14

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S776000

Reexamination Certificate

active

07000176

ABSTRACT:
A path parity error signal may be calculated by determining an inputted payload signal, determining a memory state, determining a previous path parity signal, determining a previous master signal, and relating them.

REFERENCES:
patent: 5257261 (1993-10-01), Parruck et al.
patent: 6493847 (2002-12-01), Sorgi et al.
patent: 6859453 (2005-02-01), Pick et al.
International Telecommunication Union, Series G: Transmission Systems and Media, Digital Systems and Networks, “Network node interface for the Synchronous Digital Hierarchy (SDH),” G.707, Oct. 2000, pp. i-164.

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