Scalable memory controller

Details Scalable memory controller Scalable memory controller

1997-05-16

1999-12-21

Nguyen, Hiep T.

Electrical computers and digital data processing systems: input/

Intrasystem connection

711170, 710131, G06F 1300

Patent

active

060062967

ABSTRACT:
A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.

REFERENCES:
patent: 5255239 (1993-10-01), Taborn et al.
patent: 5522059 (1996-05-01), Marushima et al.
patent: 5613152 (1997-03-01), Van Meerberger et al.
patent: 5802580 (1998-09-01), McAlpine
patent: 5841775 (1998-11-01), Huang

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