Scalable memory

Details Scalable memory Scalable memory

2006-09-12

2006-09-12

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S111000, C711S172000, C711S170000

Reexamination Certificate

active

07107399

ABSTRACT:
A memory structure and method for handling memory requests from a processor and for returning correspondence responses to the processor from various levels of the memory structure. The memory levels of the memory structure are interconnected by a forward and return path with the return path having twice the bandwidth of the forward path. An algorithm is used to determine how many responses are sent from each memory level on the return path to the processor. This algorithm is designed to guarantee a constant bound on the rate of responses sent to the processor. More specifically, if a write request is at the same level to which it is targeted, or if a request at a memory level is targeted to a higher memory level, then two responses are forwarded from a controller at the memory level on the return path to the processor. Otherwise, only one response is forwarded from the memory level on the return path.

REFERENCES:
patent: 5357621 (1994-10-01), Cox
patent: 6109929 (2000-08-01), Jasper
patent: 6425064 (2002-07-01), Soderquist
patent: WO 99/30240 (1999-06-01), None

Affiliated with

Also associated with

Rating

Scalable memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalable memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3597005