Scalable high-speed precision frequency and phase synthesis

Details Scalable high-speed precision frequency and phase synthesis Scalable high-speed precision frequency and phase synthesis

2005-09-06

2005-09-06

Ghebretinsae, Temesghen (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000, C327S156000, C708S271000

Reexamination Certificate

active

06940937

ABSTRACT:
A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a,40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a,40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2). In another embodiment, more than two adder and register units (55) control corresponding multiplexers (56) for selecting clock phases from the voltage-controlled oscillator (30) for application to an output multiplexer (58), which is controlled by a clock control circuit (60) to apply the selected clock phases to the T flip-flop (62). In another embodiment, primary and phase-shifted frequency synthesis circuits (227, 327) receive initialization values (INIT1, INIT2) that establish the phase differential and ensure proper initialization.

REFERENCES:
patent: 5126960 (1992-06-01), Thong
patent: 5841387 (1998-11-01), VanBuskirk
patent: 6329850 (2001-12-01), Mair et al.
A “Flying-Adder” Architecture of frequency and Phase Synthesis With Scalability. Xiu et al IEEE vol. 10 No. 5 Oct. 2002. pp. 637-649.
Mair and Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Sol. State Circ., vol. 35, No. 6 (IEEE, Jun., 2000), pp. 835-846.

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