Scalable high density non-volatile memory cells in a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29300

Reexamination Certificate

active

11044703

ABSTRACT:
A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is comprised of either a floating gate or a charge trapping layer over a tunnel insulator. A plurality of silicon rich nitride layers are formed over the floating gate or charge trapping layer and separated by a high dielectric constant layer.

REFERENCES:
patent: 4929988 (1990-05-01), Yoshikawa
patent: 5338953 (1994-08-01), Wake
patent: 5386132 (1995-01-01), Wong
patent: 5467305 (1995-11-01), Bertin et al.
patent: 5943267 (1999-08-01), Sekariapuram et al.
patent: 6794764 (2004-09-01), Kamal et al.
patent: 6878991 (2005-04-01), Forbes
patent: 2003/0227048 (2003-12-01), Kianian
patent: 2004/0121540 (2004-06-01), Lin
patent: 2005/0224861 (2005-10-01), Lee et al.
patent: 2005/0269626 (2005-12-01), Forbes
Mitsu Koyanagi et al.; Metal Nano-Dot Memory for High Density Non-Volatile Memory Application; 2004; Department of Bioengineering and Robotics; Tohoku University.
Cheng-Yuan Hsu et al.; Split-Gate NAND Flash Memory at 120nm Technology Node Featuring Fast Programming Erase; 2004; VLSI Technical Digest; pp. 78-79.
F. Ito et al.,; A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications; 2004; VLSI Technical Digest; pp. 80-81.
Meng-Yi Wu et al.,; Highly Scaliable Ballistic-injection And (BiAND) Flash Memory; 2004; IEDM; To be published; Micro electronic Laboratory, Semiconductor Technology Application Research Group, Department of Electrical Engineering, National Tsing-Hua University.
T. Terano et al.,; Narrow Distribution of Threshold Voltages in 4Mbit MONOS Memory-Cell Arrays and its Impact on Cell Operation; IEDM; 2001; pp. 45-48.
Dana Lee et al.,; Vertical floating-gate 4.5F2Split-gate NOR Flash Memory at 110nm Node; VLSI Technical Digest; 2004; pp. 72-73.
D.J. DiMaria et al.,; Charge transport and trapping phenomena in off-stoichiometric silicon dioxide films; JAP; vol. 54; #10; pp. 5801-5827; 1983.
T. Ishimaru et al.,; Impact of SiON on Embedded Nonvolatile MNOS Memory; IEDM, to be published, 2004, Central Research Laboratory, Hitachi Ltd.
T. Endoh et al.; Novel Ultra High Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell; The Research Institute of Electrical Communication, TOHOKU University, Sendai, Japan; 2001; pp. 2.3.1-2.3.4.

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