Scalable hierarchical I/O line structure for a semiconductor...

Details Scalable hierarchical I/O line structure for a semiconductor... Scalable hierarchical I/O line structure for a semiconductor...

2005-03-22

2005-03-22

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S296000, C257S297000, C257S365000, C257S288000, C257S206000, C257S208000

Reexamination Certificate

active

06870205

ABSTRACT:
A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

REFERENCES:
patent: 20030058685 (2003-03-01), Tran et al.

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