Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-01
2002-10-08
Chaudhari, Chandra (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S320000, C257S326000
Reexamination Certificate
active
06462375
ABSTRACT:
FIELD OF INVENTION
The present invention relates in general to a flash memory cell and its memory array and, more particularly, to a scalable dual-bit flash memory cell and its contactless flash memory array for high-density mass storage applications.
DESCRIPTION OF THE RELATED ART
A stack-gate flash memory cell is known to be a one-transistor cell, in which the gate length of a cell can be defined by using the minimum-feature-size (F) of technology used. Therefore, the stack-gate flash memory cell is often used in existing high-density flash memory system. Basically, the stack-gate flash memory cells can be interconnected to form different configurations based on the basic logic function, such as NOR, NAND and AND.
The NAND-type flash memory array is formed by interconnecting stack-gate flash memory cells in series with common-source/drain diffusion regions. The density of a NAND-type flash memory array is high, however the read speed is slow for a NAND-type flash memory array due to the series resistance of the configuration. Moreover, a NAND-type flash memory cell is programmed by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common-source/drain diffusion region and its programming speed is relatively slow.
The NOR-type flash memory array is connected with the common-source diffusion lines and each of the common-drain diffusion regions in each column being connected to a bit line through contacts. The read speed of a NOR-type flash memory array is much faster as compared to that of a NAND-type flash memory array. Moreover, a stack-gate flash memory cell in a NOR-type flash memory array is in general programmed by channel hot-electron injection and its programming speed is much faster than that of a NAND-type flash memory array. However, the cell size of a NOR-type flash memory array is about twice as compared to that of a NAND-type flash memory array due to the bit-line contact. Moreover, the programming power is larger and the programming efficiency is low for a NOR-type flash memory array due to the channel hot-electron injection as the programming method.
Another array architecture, which takes advantages of both NOR-type and NAND-type arrays, is shown in
FIG. 1
, in which
FIG. 1A
shows a cross-sectional view of a dual-bit flash memory cell and
FIG. 1B
shows a top plan view of FIG.
1
A. As shown in FIG.
1
A(
a
) and FIG.
1
B(
b
), a gate region of a dual-bit flash memory cell including two stack-gate transistors
22
G,
20
G and a select-gate transistor
24
G is formed on a semiconductor substrate
26
, in which two common N
+
/N
−
diffusion regions
22
A,
20
A are formed in the semiconductor substrate
26
outside of the gate region ; a select-gate line (SG) is formed above two common N
+
/N
−
diffusion regions and two stack-gate transistors and on a gate dielectric layer
24
A being formed on a semiconductor substrate
26
. Since the stack-gate transistor, the select-gate transistor and the common N
+
/N
−
diffusion region can be defined by a masking photoresist step with a minimum-feature-size F, the cell size of each bit in a dual-bit flash memory cell is 4 F
2
if the select-gate line and its space can be defined to be a minimum-feature-size F. Apparently, the cell size of
FIG. 1
can be made to be comparable to that of a NAND-type flash memory array due to the contactless structure; the read speed of
FIG. 1
is much better than that of a NAND-type flash memory array; the programming power and the programming efficiency is much better than that of a NOR-type flash memory array. However, there are several drawbacks that can be easily observed: very high capacitance between the select-gate line (SG) and the common N
+
/N
−
diffusion regions
22
A,
20
A; very high capacitance between the select-gate line (SG) and the control-gate lines
22
C,
20
C; isolation between the common N
+
/N
−
diffusion regions is poor for the regions outside of the select-gate region
24
A; and isolation between nearby select-gate lines is very poor for the regions under the control-gate lines
22
C,
20
C. It should be emphasized that poor isolation between nearby select-gate lines may result in an erroneous data reading from nearby cells under the same control-gate line.
It is therefore an objective of the present invention to provide a scalable dual-bit flash memory cell having a cell size of each bit being smaller than 2 F
2
.
It is another objective of the present invention to provide a shallow-trench-isolation structure for scalable dual-bit flash memory cells in nearby rows of an array.
It is further objective of the present invention to provide two common-source and drain conductive bus-lines for a scalable dual-bit flash memory cell with much smaller bus-line resistances and bus-line parasitic capacitances with respect to the semiconductor substrate and the word lines.
It is yet another objective of the present invention to provide a low-voltage select-gate structure for a scalable dual-bit flash memory cell.
Other objectives and advantages of the present invention will be more apparent from the following description.
SUMMARY OF THE INVENTION
A scalable dual-bit flash memory cell and its contactless flash memory array are disclosed by the present invention. The scalable dual-bit flash memory cell is formed on a semiconductor substrate of a first conductivity type having an active region formed between two shallow-trench-isolation (STI) regions, wherein the active region has a first conductive layer formed on a first gate-dielectric layer and each of STI regions has a raised field-oxide layer. The scalable dual-bit flash memory cell can be divided into three regions: a first-side region, a gate region, and a second-side region, in which the gate region is located between the first-side region and the second-side region. The first/second-side region comprises a first sidewall dielectric spacer being formed over each sidewall of the gate region and on a portion of a first/second flat bed formed by a common-source/drain diffusion region of a second conductivity type and its nearby etched raised field-oxide layers; a common-source/drain conductive bus line being formed on the first/second flat bed outside of the first sidewall dielectric spacer; and a planarized thick-oxide layer being formed over the common-source/drain conductive bus line and the first sidewall dielectric spacer. The gate region of the first embodiment comprises a pair of second sidewall dielectric spacers being formed over each sidewall of the first sidewall dielectric spacer in the first/second-side region and on the first conductive layer in the active region and the raised field-oxide layers in the STI regions; a pair of floating-gate layers being formed in the active region and being patterned by the pair of second sidewall dielectric spacers; an implant region of the first conductivity type being formed in the semiconductor substrate of the active region between the pair of floating-gate layers; and a planarized control-gate layer over a second gate-dielectric layer being formed over the exposed surfaces of the pair of second sidewall dielectric spacers, the pair of floating-gate layers, the raised field-oxide-layers, and a semiconductor surface of the implanted region. The gate region of the second embodiment comprises a pair of floating-gate layers being patterned by the pair of second sidewall dielectric spacers; an implant region of the first conductivity type being formed in the semiconductor substrate of the active region between the pair of floating-gate layers; and a planarized control-gate layer over a second gate-dielectric layer being formed over the exposed surfaces of the pair of floating-gate layers, the raised field-oxide layers, and a semiconductor surface of the implanted region. A first interconnect-metal layer is formed over the planarized thick-oxide layers or the second gate-dielectric layer in the first/second-side regions and the planarized control-gate layer in the g
Chaudhari Chandra
Silicon Based Technology Corp.
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