Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-01-14
2009-10-13
Auve, Glenn A (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S310000
Reexamination Certificate
active
07603508
ABSTRACT:
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
REFERENCES:
patent: 4014005 (1977-03-01), Fox et al.
patent: 4968977 (1990-11-01), Chinnaswamy et al.
patent: 5634076 (1997-05-01), Garde et al.
patent: 5708849 (1998-01-01), Coke et al.
patent: 6014709 (2000-01-01), Gulick et al.
patent: 6049845 (2000-04-01), Bauman et al.
patent: 6108738 (2000-08-01), Chambers et al.
patent: 6138185 (2000-10-01), Nelson et al.
patent: 6154794 (2000-11-01), Abdalla et al.
patent: 6167489 (2000-12-01), Bauman et al.
patent: 6182112 (2001-01-01), Malek et al.
patent: 6185221 (2001-02-01), Aybay
patent: 6247100 (2001-06-01), Drehmel et al.
patent: 6289376 (2001-09-01), Taylor et al.
patent: 6292705 (2001-09-01), Wang et al.
patent: 6314501 (2001-11-01), Gulick et al.
patent: 6356983 (2002-03-01), Parks
patent: 6415424 (2002-07-01), Arimilli et al.
patent: 6490585 (2002-12-01), Hanson et al.
patent: 6546451 (2003-04-01), Venkataraman et al.
patent: 6549961 (2003-04-01), Kloth
patent: 6622182 (2003-09-01), Miller et al.
patent: 6651131 (2003-11-01), Chong et al.
patent: 6665761 (2003-12-01), Svenkeson et al.
patent: 6728206 (2004-04-01), Carlson
patent: 7058750 (2006-06-01), Rankin et al.
patent: 7206869 (2007-04-01), Shishizuka et al.
patent: 7343442 (2008-03-01), Rankin et al.
patent: 2007/0106833 (2007-05-01), Rankin et al.
U.S. Appl. No. 09/569,100 Final office action mailed Feb. 26, 2004, 13 pgs.
U.S. Appl. No. 09/569,100 “Non-final office action mailed May 15, 2003”, 11 pgs.
U.S. Appl. No. 09/569,100 “Non-final office action mailed May 31, 2005”, 8 pgs.
U.S. Appl. No. 09/569,100 “Non-final office action mailed Aug. 22, 2002”, 10 pgs.
U.S. Appl. No. 09/569,100 “Notice of allowance mailed Jan. 13, 2006”, 6 pgs.
U.S. Appl. No. 09/569,100 “Response filed Nov. 17, 2003 to non-final office action mailed May 15, 2003”, 12 pgs.
U.S. Appl. No. 09/569,100 Response filed Nov. 30, 2005 to non-final office action mailed May 31, 2005, 41 pgs.
“U.S. Appl. No. 09/569,100, Response filed Feb. 24, 2003, in response to Non-Final Office Action mailed Aug. 22, 2002”, 11 pgs.
“U.S. Appl. No. 09/569,100 Response filed Mar. 30, 2005, in response to Final Office Action mailed Feb. 26, 2004”, 14 pgs.
“U.S. Appl. No. 11/422,542 Non-Final Office Action mailed Mar. 14, 2007”, 7 pgs.
“U.S. Appl. No. 11/422,542 Notice of Allowance mailed Jun. 14, 2007”, 4 pgs.
“U.S. Appl. No. 11/422,542 Preliminary Amendment Filed Jan. 24, 2007”, 10 pgs.
“U.S. Appl. No. 11/422,542 Response filed May 14, 2007 in response to Non-Final Office Action mailed Mar. 14, 2007”, 7 pgs.
U.S. Appl. No. 11/422,542 “Supplemental Notice of Allowability mailed Jul. 19, 2007”, 5 pgs.
U.S. Appl. No. 11/422,542 “Notice of Allowance mailed Oct. 11, 2007”, 7 pgs.
Borkar Nitin Y.
Cheng Kai
Dermer Gregory E.
Hofsheier Richard H.
Pierce Paul R.
Auve Glenn A
Intel Corporation
Schwegman Lundberg & Woessner, P.A.
LandOfFree
Scalable distributed memory and I/O multiprocessor systems... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scalable distributed memory and I/O multiprocessor systems..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable distributed memory and I/O multiprocessor systems... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4126436