Scalable design for DDR SDRAM buses

Details Scalable design for DDR SDRAM buses Scalable design for DDR SDRAM buses

2005-09-13

2005-09-13

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C713S322000

Reexamination Certificate

active

06944738

ABSTRACT:
A memory subsystem and a method for use in accessing a memory system are disclosed. The memory subsystem comprising a plurality of SDRAM memory modules and a memory controller. The memory controller is capable of waiting to generate a memory clock signal for each of the SDRAM memory modules until a valid window for a control signal and an address signal; generating the memory clock signals during the valid window, and generating the control and address signals. The method comprises: waiting for a valid window for a control signal and an address signal; generating a memory clock during the valid window; and generating the control signal and the command signal a predetermined period of time after generating the memory clock signal.

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