Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2006-09-05
2006-09-05
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07103832
ABSTRACT:
A CRC circuit, CRC method, and method of designing a CRC circuit, the CRC circuit, including: a packet data slice latch having outputs; a multiple level XOR subtree, each level including one or more XOR subtrees, each output of the packet data slice latch coupled to an input of the multiple level XOR subtree, each lower level XOR subtree coupled to a higher level XOR subtree through an intervening latch level; a remainder XOR subtree; a combinational XOR subtree, the outputs of the remainder XOR subtree and the outputs of the multiple level XOR subtree coupled to the inputs of the combinational XOR subtree; and a current CRC result latch, the output of the combinational XOR subtree coupled to the inputs of the current CRC result latch and the outputs of the M-bit current CRC result latch coupled to the inputs of the remainder XOR subtree.
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IBM Technical Disclosure Bulletin, Nielson et al., Byte-Wide ECC/CRC Code and Syndrome Calculator, vol. 29, No. 5, Oct. 1986, pp. 2141-2145.
Leonard Todd E.
Mann Gregory J.
Baker Stephen M.
Schmeiser Olsen & Watts
Steinberg William H.
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