Scalable crossbar switch

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C370S412000, C370S413000

Reexamination Certificate

active

06557070

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to crossbar switches that are scalable and may be increased in size by coupling together smaller crossbar switch elements as building blocks.
BACKGROUND INFORMATION
Crossbar switching fabrics (the way signals are routed from input to output) are inherently easy to understand and are well documented in the literature. With their long legacy in voice systems which started with the crossbar central office, circa 1930, they are well known to those in the switching business, hence they are often looked at as quick entry points into the data switching environment.
Some crossbar switches have the advantage in that they are typically non-blocking. This means that when a particular input path is connected to an output path the other inputs and outputs are available for connection. In non-blocking crossbar switches, the “made” connection does not interfere with those remaining. When a crossbar switch is used for data switching applications, requirements within the data communication protocols put added burdens on the crossbar switch creating two fundamental problems. The first problem is how to schedule the switching fabric to take advantage of the variable size packets coming through the switching fabric and hence maximize the throughput. This problem is addressed by a technique called a “scheduled crossbar” which is being worked on by several researchers in the field and is not addressed in this disclosure. The second problem deals with issues that result if multiple single switch element building blocks are combined to make a larger, scalable switching fabric. Scaling crossbar switches in voice systems, especially using electromechanical switches or individual transistors, was relatively easy.
FIGS. 1A and 1B
illustrate how a basic switch element for voice systems was used to make a larger switch fabric. The switch building block
101
is used (in groups of four) to build a switching fabric
106
with a capacity twice that of an individual switch building block
101
. Switch building blocks
102
,
103
,
104
and
105
are coupled to form crossbar switch fabric
106
. Scaling the crossbar switch fabrics, illustrated in
FIG. 1
, has no inherent disadvantages because once a connection is set up there are essentially no delays, other than wiring delays, added to the switching fabric
106
.
However, in a data switching fabric, it is necessary to provide some buffering or queuing at the input and output to the switching fabric to handle issues such as address lookup/manipulation, handling multicast and broadcast messages, etc. A single crossbar switch chip designed for data communication may lead to single switch element
201
as shown in FIG.
2
A. The previously described buffering (queuing structure) is shown in FIG.
2
A and
FIG. 2B
as the open-ended rectangles, input queue
207
and output queue
214
. When multiples of single switch element
201
(e.g., switch elements
203
,
204
,
205
,
209
) are used to scale up a switching fabric
206
as shown in
FIG. 2B
, excess buffering or queuing is introduced internal to the overall switch fabric
206
which adds significant latency thus degrading switching fabric performance while providing no additional functional value. For example, output queue
213
is in series with output queue
208
and input queue
209
is in series with input queue
210
. The switch element
201
is typically an integrated circuit chip incorporating the logic, switching, and queuing or buffering needed for a “N×N” switch element. These switch chips are then typically assembled on a printed circuit card to form a larger crossbar data communication switch.
Since it is desirable to make a single crossbar switch chip as the building block for making variable width crossbar switch fabrics for data communication, there is a need for a method to overcome the problem of scaling which would introduce unnecessary buffering delays.
SUMMARY OF THE INVENTION
A scalable crossbar switch is enabled by a single crossbar switch chip that is used to make variable sized crossbar switch fabrics. The single crossbar switch chip has input and output queuing necessary for handling data communication. The single crossbar switch chip also has drivers placed after output queuing and after input queuing.
Although the number (N) of switch chips are continuously expandable, i.e., 2, 3, 4, 5, switches are scaled by assembling in groups based on N squared. A switch fabric may comprise one, four, nine, sixteen, etc. chips. When switch assemblies are constructed using multiples of the switch chip, the switch chip outputs that couple to the inputs of another switch chip have their output queuing bypassed so the output drivers may drive off-chip loads without degrading performance by adding latency. Likewise inputs of one switch chip coupled to the outputs of another switch chip have their input queuing disabled or bypassed so queuing is done only once. The individual switch chips making up a larger crossbar switch assembly have configuration inputs that are selectively coupled to voltages that activate insertion or the bypassing of the queuing circuits. Which queuing circuits are bypassed is determined by where a particular switch chip is placed on a circuit board used to wire the switch chips into the larger crossbar switch assembly. In this manner, a larger crossbar switch may be made with a single switch design minimizing queuing delays and maintaining line driver buffering for all off chip outputs.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 5189665 (1993-02-01), Niehaus et al.
patent: 5309426 (1994-05-01), Crouse et al.
patent: 5537400 (1996-07-01), Diaz et al.
patent: 5623698 (1997-04-01), Stephenson et al.
patent: 5636210 (1997-06-01), Agrawal
patent: 5745489 (1998-04-01), Diaz et al.
patent: 5898692 (1999-04-01), Dunning et al.
patent: 6167489 (2000-12-01), Bauman et al.
patent: WO 99/11033 (1999-03-01), None
“Lookaside Input Buffer for Packet Switching”, IBM Technical Disclosure Bulletin, Aug. 1985, vol. 28, No. 3, pp. 1255-1259.*
“Scalable, Modular, Interconnection Cache Network Structure for Temporarily Localized Communication Requests,”IBM Technical Disclosure Bulletin, vol. 34 No. 10A, Mar. 1992, pp. 66-68.

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