Scalable cross bar type storage controller

Details Scalable cross bar type storage controller Scalable cross bar type storage controller

1996-12-30

1999-09-28

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711153, G06F 1208

Patent

active

059604557

ABSTRACT:
Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.

REFERENCES:
patent: 3641505 (1972-02-01), Artz et al.
patent: 3812469 (1974-05-01), Hauck et al.
patent: 3872447 (1975-03-01), Tessera et al.
patent: 4056844 (1977-11-01), Izumi
patent: 4070704 (1978-01-01), Calle et al.
patent: 4130865 (1978-12-01), Heart et al.
patent: 4245306 (1981-01-01), Besemer et al.
patent: 4349871 (1982-09-01), Lary
patent: 4426681 (1984-01-01), Bacot et al.
patent: 4437157 (1984-03-01), Witalka et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4445174 (1984-04-01), Fletcher
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4525777 (1985-06-01), Webster et al.
patent: 4551799 (1985-11-01), Ryan et al.
patent: 4586133 (1986-04-01), Steckler
patent: 4667288 (1987-05-01), Keeley et al.
patent: 4701844 (1987-10-01), Thompson et al.
patent: 4707784 (1987-11-01), Ryan et al.
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4761755 (1988-08-01), Ardini, Jr. et al.
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 4843541 (1989-06-01), Bean et al.
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 4860192 (1989-08-01), Sachs et al.
patent: 4868818 (1989-09-01), Madan et al.
patent: 4888771 (1989-12-01), Benignus et al.
patent: 4891810 (1990-01-01), de Corlieu et al.
patent: 4979107 (1990-12-01), Advani et al.
patent: 4984153 (1991-01-01), Kregness et al.
patent: 4985829 (1991-01-01), Thatte et al.
patent: 4992930 (1991-02-01), Gilfeather et al.
patent: 4992934 (1991-02-01), Portanova et al.
patent: 4995035 (1991-02-01), Cole et al.
patent: 5014197 (1991-05-01), Wolf
patent: 5023776 (1991-06-01), Gregor
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5025366 (1991-06-01), Baror
patent: 5029070 (1991-07-01), McCarthy et al.
patent: 5043874 (1991-08-01), Gagliardo et al.
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5095424 (1992-03-01), Woffinden et al.
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5148533 (1992-09-01), Joyce et al.
patent: 5193163 (1993-03-01), Sanders et al.
patent: 5197139 (1993-03-01), Emma et al.
patent: 5206945 (1993-04-01), Nishimukai et al.
patent: 5212781 (1993-05-01), Shah
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5222244 (1993-06-01), Carbine et al.
patent: 5241641 (1993-08-01), Iwasa et al.
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5313602 (1994-05-01), Nakamura
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5359723 (1994-10-01), Matthews et al.
patent: 5386547 (1995-01-01), Jouppi
patent: 5392416 (1995-02-01), Doi et al.
patent: 5423016 (1995-06-01), Tsuchiya et al.
patent: 5490261 (1996-02-01), Bean et al.
patent: 5519846 (1996-05-01), Swenson
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5555382 (1996-09-01), Thaller et al.
patent: 5574944 (1996-11-01), Stager
patent: 5577259 (1996-11-01), Alferness et al.
patent: 5603005 (1997-02-01), Bauman et al.
Dubois et al., "Effects of Cache Coherency in multiprocessors", IEEE Transactions on Computers, vol. C-31, No. 11, Nov. 1982, pp. 1083-1099.
Wilson, Jr., "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors", IEEE, 1987, pp. 244-252.
Sparacio, "Data Processing System With Second Level Cache", IBM Technical Disclosure Bulletin, vol. 21, No. 6, Nov. 1978, pp. 2468-2469.
Myers et al., The 80960 Microprocessor Architecture, 1988, pp. 159-183.
Hinton et al., "Microarchitecture of the 80960 High-Integration Processors", Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors--ICCD, 1988, pp. 362-365.
Bandyopadhyay et al., "Combining Both Micro-Code and Hardwired Control in RISC", Computer Architecture News, 1990, pp. 11-15.
Bandyopadhyay et al., "Micro-Code Based RISC Architecture", 19th Southeastern Symposium on System Theory, Mar. 1987, pp. 411-414.

Affiliated with

Also associated with

Rating

Scalable cross bar type storage controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalable cross bar type storage controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable cross bar type storage controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-716307