Scalable cache coherent distributed shared memory processing...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S151000, C711S156000

Reexamination Certificate

active

06944719

ABSTRACT:
A packetized I/O link such as the HyperTransport protocol is adapted to transport memory coherency transactions over the link to support cache coherency in distributed shared memory systems. The I/O link protocol is adapted to include additional virtual channels that can carry command packets for coherency transactions over the link in a format that is acceptable to the I/O protocol. The coherency transactions support cache coherency between processing nodes interconnected by the link. Each processing node may include processing resources that themselves share memory, such as symmetrical multiprocessor configuration. In this case, coherency will have to be maintained both at the intranode level as well as the internode level. A remote line directory is maintained by each processing node so that it can track the state and location of all of the lines from its local memory that have been provided to other remote nodes. A node controller initiates transactions over the link in response to local transactions initiated within itself, and initiates transactions over the link based on local transactions initiated within itself. Flow control is provided for each of the coherency virtual channels either by software through credits or through a buffer free command packet that is sent to a source node by a target node indicating the availability of virtual channel buffering for that channel.

REFERENCES:
patent: 5526510 (1996-06-01), Akkary et al.
patent: 6314498 (2001-11-01), Arimilli et al.
patent: 2003/0023814 (2003-01-01), Barroso et al.
patent: 2003/0115423 (2003-06-01), Chang

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