Scalable bus structure

Details Scalable bus structure Scalable bus structure

2007-04-24

2007-04-24

Myers, Paul R. (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S110000, C710S113000, C710S310000, C710S022000, C370S276000, C370S438000, C370S395100

Reexamination Certificate

active

10921053

ABSTRACT:
A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

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IBM 64-Bit Processor Local Bus—Architecture Specifications, Version 3.5—May 2001—selected pages are attached (pp. 1, 2, 4, 32, 33, 52, 61)—entire specification can be obtained at the following website owned by IBM: http://www-3.ibm.com/chips/techlib/techlib.nsf/%20techdocs/8BA965C773B2E0ED87256AB20082CC9F.
InfiniBandSMTrade Association. InfiniBand™ Architecture Specification vol. 1. Release 1.0.a. Jun. 19, 2001. pp. 2; 38-46.

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