Sampling-error phase compensating apparatus and method thereof

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C327S141000, C358S409000, C358S410000, C370S503000, C713S400000, C714S012000

Reexamination Certificate

active

07453971

ABSTRACT:
A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals. The method sequentially includes: sampling each data signal according to a first sampling clock signal, and sequentially outputting corresponding phase detection signals according to the sampled data signals; sequentially outputting phase regulating signals, which correspond to the phase detection signals, respectively, according to the phase detection signals, wherein when the phase detection signals are the same, the phase regulating signals includes first-state phase regulating signals and second-state phase regulating signals, the first-state phase regulating signals correspond to the phase detection signals, and the number of the second-state phase regulating signals is smaller than that of the first-state phase regulating signals; and sequentially outputting second sampling clock signals according to the phase regulating signals, wherein phases of the sampling clock signals correspond to those of the phase regulating signals, respectively.

REFERENCES:
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patent: 5450452 (1995-09-01), Kakuishi et al.
patent: 5905769 (1999-05-01), Lee et al.
patent: 6573698 (2003-06-01), Eto
patent: 6959062 (2005-10-01), Stubbs

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