Sampling clock generator circuit and data receiver using the...

Details Sampling clock generator circuit and data receiver using the... Sampling clock generator circuit and data receiver using the...

2007-06-19

2007-06-19

Ghebretinsae, Temesghen (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C331S057000

Reexamination Certificate

active

10054964

ABSTRACT:
A sampling clock generator circuit comprises a ring oscillator including series-connected m first inverters connected to a first power supply line, where m is an odd number equal to or larger than 3, a delay line including series-connected 2m or 2m−1 second inverters connected to a second power supply line, for delaying an externally supplied clock, and a PLL circuit for controlling an oscillation frequency of the ring oscillator by controlling a voltage of the first power supply line by using the ring oscillator as a voltage controlled oscillation circuit. A voltage of the second power supply line is set substantially equal to the voltage of the first power supply line and the delayed clock obtained by the second inverters is used as a sampling clock.

REFERENCES:
patent: 5239274 (1993-08-01), Chi
patent: 6683503 (2004-01-01), Mizuno et al.
patent: 4-20016 (1992-01-01), None

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