Sampled amplitude read channel employing pipelined reads to...

Details Sampled amplitude read channel employing pipelined reads to... Sampled amplitude read channel employing pipelined reads to...

1997-03-12

2003-11-11

Faber, Alan T. (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S067000, C360S051000, C360S065000, C360S066000

Reexamination Certificate

active

06646822

ABSTRACT:

FIELD OF INVENTION
The present invention relates to the control of magnetic storage systems for digital computers, and particularly, to discrete time circuitry integrated into a sampled amplitude read channel for synchronous detection of user data and embedded servo data.
CROSS REFERENCE TO RELATED APPLICATIONS AND PATENTS
This application is related to several U.S. patents, namely U.S. Pat. No. 5,424,881 entitled “Synchronous Read Channel,” U.S. Pat. No. 5,359,631 entitled “Timing Recovery Circuit for Synchronous Waveform Sampling,” U.S. Pat. No. 5,291,499 entitled “Method and Apparatus for Reduced-Complexity Viterbi-Type Sequence Detectors,” U.S. Pat. No. 5,297,184 entitled “Gain Control Circuit for Synchronous Waveform Sampling,” and U.S. Pat. No. 5,329,554 entitled “Digital Pulse Detector.” All of the above-named patents are assigned to the same entity, and all are incorporated herein by reference.
BACKGROUND OF THE INVENTION
In magnetic disk storage systems for computers, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written onto a magnetic medium in concentric tracks. To read this recorded data, the read/write head passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog signal that alternate in polarity. These pulses are then decoded by read channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and, are less susceptible to noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
In conventional peak detection schemes, analog circuitry, responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head. The analog read signal is “segmented” into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a “1” bit, whereas the absence of a peak is detected as a “0” bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive “0” bits.
As the pulses are packed closer together on the concentric data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. The ISI effect is reduced by decreasing the data density or by employing an encoding scheme to ensure that a minimum number of “0” bits occur between “1” bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of “0” bits between “1” bits, and to k the maximum number of consecutive “0” bits. A typical RLL code is a (
1
,
7
) ⅔ rate code which encodes 8 bit data words into 12 bit codewords to satisfy the (
1
,
7
) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and increasing channel noise immunity. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. The analog pulses are sampled at the baud rate (code bit rate) and the digital data is detected from these discrete time sample values. A discrete time sequence detector, such as a Viterbi detector, interprets the discrete time sample values in context to determine a most likely sequence for the data. In this manner, the effect of ISI can be taken into account during the detection process, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, “Partial Response Signaling”,
IEEE Trans. Commun. Tech
., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, “Digital Communication”, Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., “The Viterbi Algorithm”, Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, “A PRML System for Digital Magnetic Recording”,
IEEE Journal on Selected Areas in Communications
, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, “Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel”,
IEEE Trans. Commun
., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, “Implementation of PRML in a Rigid Disk Drive”,
IEEE Trans. on Magnetics
, Vol. 27, No. 6, November 1991; and Carley et al, “Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection”,
Digest of The Magnetic Recording Conference
, Aug. 15-17, 1994, pp. C3; and Moon et al, “Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback”,
IEEE Trans. on Magnetics
, Vol. 30, No. 5, September 1994; and Abbott et al, “Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel”,
Globecom
'90
IEEE Global Telecommunications Conference
1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, “Performance of Digital Magnetic Recording with Equalization and Offtrack Interference”,
IEEE Transactions on Magnetics
, Vol. 27, No. 1, January 1991; and Cioffi et al, “Adaptive Equalization in Magnetic-Disk Storage Channels”,
IEEE Communication Magazine
, February 1990; and Roger Wood, “Enhanced Decision Feedback Equalization”,
Intermag
'90.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods, as in peak detection systems, sampled amplitude systems synchronize the sampling of the pulses to the baud rate. That is, timing recovery adjusts the sampling clock in order to minimize the error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
The decision-directed feedback system is normally implemented using a phase-locked-loop (PLL) circuit comprising a phase detector for generating a phase error based on the difference between the estimated samples and the read signal samples. A loop filter filters the phase error, and

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