Sample wafer fabrication method

Details Sample wafer fabrication method Sample wafer fabrication method

2011-01-11

2011-01-11

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S232000, C438S275000, C438S527000, C438S942000, C438S948000, C257S500000, C257SE21317, C257SE21633

Reexamination Certificate

active

07867884

ABSTRACT:
A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity concentration of the first channel regions, a third step of forming a plurality of third channel regions in a third region on the surface of the water, and a fourth step of forming a plurality of fourth channel regions having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region, wherein the first region and the second region are divided by a first line segment on the wafer, and the third and fourth regions are divided by a second line segment intersecting with the first line segment on the wafer.

REFERENCES:
patent: 5795803 (1998-08-01), Takamura et al.
Carver Mead (author), Shiro Usui and Hiroo Yonezu (translators) “Analog VLSI and Neural System”, Toppan Printing Co., Ltd. Appendix CMOS fabrication method.

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