Sample selection and data alignment circuit

Details Sample selection and data alignment circuit Sample selection and data alignment circuit

2006-11-14

2006-11-14

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000, C375S326000, C375S355000, C375S362000, C370S516000, C370S518000, C713S400000, C713S503000

Reexamination Certificate

active

07136443

ABSTRACT:
There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G0, . . . , Gn−1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G0, . . . , Gn−1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G0, . . . , Gn−1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

REFERENCES:
patent: 5487095 (1996-01-01), Jordan et al.
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patent: 6026134 (2000-02-01), Duffy et al.
patent: 6556583 (2003-04-01), Hayashi et al.
patent: 2003/0021368 (2003-01-01), Yoshizaki
Vallet et al., IBM, filed concurrently herewith, entitled “Method and Circuit for Recovering a Data signal from a Stream of Binary Data”.
Vallet et al., IBM, filed concurrently herewith, entitled “Transition Detection, Validation and Memorization Circuit”.

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