Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-05-03
2004-10-12
Zaneke, Danil A. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010
Reexamination Certificate
active
06803780
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sample chuck or work piece for holding essentially flat samples, such as semiconductor wafers.
2. Background Art
Sample chucks have flat surfaces for receiving and holding samples, often semiconductor wafers, within equipment for processing or measurement purposes. Sample chucks are, for example, an integral component in measurement systems utilized to process semiconductor wafers. They are also used in products and in other equipment, such as photolithographic tools.
Sample chucks may perform a mechanical function, such as precisely holding a sample, or they may be used to move a sample, or they may be used to make controlled electrical contact to a sample. Occasionally, a chuck may be called upon to perform multiple functions.
Currently, sample chucks are constructed of ceramic materials, machined metals or semiconductor slabs. When formed from ceramic materials, sample chucks can be made having good flatness. However, sample chucks formed from ceramic materials form poor contact with a sample and such chucks have potential weight problems. When formed from machined metals, sample chucks have acceptable flatness and form good contact with samples. However, sample chucks formed from machined metals are susceptible to imparting contaminants to a sample, especially a sample semiconductor wafer. When formed from semiconductor slabs, sample chucks can be made having good flatness and minimal contaminants. However, sample chucks formed from semiconductor slabs are expensive to produce due to the requirement for a large slab of uniform material and the limitation on machining complex structures.
There is presently a need for a sample chuck which combines the best features of the chucks formed from ceramic materials, machined metals and semiconductor slabs, without having their respective drawbacks.
It is, therefore, an object of the present invention to provide a sample chuck where the parameters of flatness, contact formation, low weight and minimal or no contaminants are optimized at reasonable cost, especially for receiving all or part of a semiconductor wafer. Still other objects of the invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.
SUMMARY OF THE INVENTION
Accordingly, we have invented a sample chuck for supporting sample semiconductor wafers during test. The sample chuck includes an upper layer formed from a semiconducting material laminated to a lower layer formed from a conducting material. A conductive bonding agent can be received between the upper and lower layers for forming a bond therebetween.
A surface of the lower layer that faces a surface of the upper layer when the upper and lower layers are laminated together can include at least one depression for receiving the bonding agent. Alternatively or additionally, a surface of the upper layer that faces a surface of the lower layer when the upper and lower layers are laminated together can include at least one depression for receiving the bonding agent.
The lower layer can include a vacuum path having a first end in fluid communication with a through-hole in the upper layer and a second end in fluid communication with a vacuum duct. The through-hole extends through the upper layer between the vacuum path and an exposed surface of the upper layer. The vacuum duct extends through the lower layer between the vacuum path and an exposed surface of the lower layer.
Preferably, the upper layer is a semiconductor wafer and the lower layer is a conductive metal that may or may not be contaminating to semiconductor wafers. Preferably, the surface of the upper layer that faces away from the lower layer is substantially planar.
A surface of the upper layer facing the lower layer can be metalized and/or doped with impurities for enhancing a conductivity of the upper layer and/or the bond between the upper layer and the lower layer.
REFERENCES:
patent: 6365436 (2002-04-01), Faraci
Adams Michael John
Alexander William J.
Howland, Jr. William H.
Nguyen Trung Q.
Solid State Measurements, Inc.
Webb Ziesenheim & Logsdon Orkin & Hanson, P.C.
Zaneke Danil A.
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