Sample and load scheme for observability of internal nodes in a

Details Sample and load scheme for observability of internal nodes in a Sample and load scheme for observability of internal nodes in a

1998-01-23

2000-01-11

Nelms, David

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

36518912, G11C 700

Patent

active

060143347

ABSTRACT:
A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

REFERENCES:
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patent: 5497475 (1996-03-01), Alapat
patent: 5568380 (1996-10-01), Brodnax et al.
patent: 5581198 (1996-12-01), Trimberger
patent: 5764079 (1998-06-01), Patel et al.
patent: 5870410 (1999-02-01), Norman et al.

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