Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate
1999-11-12
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
C326S040000
Reexamination Certificate
active
06243304
ABSTRACT:
RELATED APPLICATIONS
The present invention is related to commonly assigned, U.S. Pat. No. 6,020,758, entitled “Partially Reconfigurable Programmable Logic Device,” by Patel et al., which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
The present invention relates in general to programmable logic circuits, and in particular to a circuit and methodology that allow the user to observe the state of internal nodes within the programmable logic circuit.
A growing trend in the field of electronic circuits and systems design is the use of prototyping or emulation systems that are built with programmable logic devices (PLDs). Such emulation systems help in debugging complex designs with quick turn-around which ensure successful time-to-market for the final product. Programmable logic devices, including programmable logic arrays (PLAs) and field programmable gate arrays (FPGAs) are particularly suited for such debug systems since they provide the flexibility required by design adjustments resulting from design errors or enhancements. Furthermore, such hardware prototyping solutions are often fast enough to operate in the context of the rest of the system. This gives the system designers a high degree of confidence.
A drawback of existing PLD-based emulation or prototyping systems, however, is that the internal state of the programmable logic devices are inaccessible and buried inside the device. This limits the troubleshooting and debugging capabilities of the system. Software based emulation systems provide for complete observability of all nodes within the system, but at the cost of running from 100 to 1 million times slower than the rest of the system.
There is therefore a need for programmable logic devices that can operate at full system speed while simultaneously providing access to observe the state of internal nodes of the device.
SUMMARY OF THE INVENTION
The present invention provides various embodiments for a programmable logic device (PLD) that allows complete observability of the states of internal nodes. Among the various internal nodes, the PLD of this invention provides observability and controllability of, for example, the state of a flip-flop inside each logic element, the state of memory bits, as well as the state of input/output (I/O) pins.
Accordingly, in one embodiment, the present invention provides a programmable logic device including a plurality of logic array blocks each having a plurality of logic elements, and a network of interconnect lines interconnecting the plurality of logic array blocks. Each logic element includes a primary register coupled to a shadow storage unit. Data buses couple a shift register to the plurality of logic array blocks. The shift register also couples to an I/O pin. In a sample mode of operation, the contents of selected primary registers are sampled into the corresponding shadow storage units, and made available on the I/O pin via the shift register. In a load mode of operation, the contents of selected shadow storage units are loaded into the corresponding primary registers.
In another embodiment, the PLD further includes memory blocks having random access memory cells. The memory cells within the memory block are made observable by a similar arrangement whereby each memory cell is provided with and coupled to a shadow storage unit.
In yet another embodiment, I/O cells around the periphery of the PLD are provided with dedicated shadow storage units as well. In a specific embodiment of the present invention, the JTAG boundary scan chain of latches are used as the shadow storage units to provide observability of the I/O cells.
A better understanding of the nature and advantages of the PLD of the present invention may be gained by reference to the detailed description and diagrams below.
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patent: 5568380 (1996-10-01), Brodnax et al.
patent: 5581198 (1996-12-01), Trimberger
patent: 5764079 (1998-06-01), Patel et al.
patent: 5870410 (1999-02-01), Norman et al.
patent: 6014334 (2000-01-01), Patel et al.
Norman Kevin A.
Patel Rakesh H.
Altera Corporation
Nelms David
Townsend and Townsend and Crew
Tran M.
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