Salicide process for FETs

Details Salicide process for FETs Salicide process for FETs

1995-07-03

1996-09-10

Fourson, George

Fishing, trapping, and vermin destroying

437186, 437200, H01L 21265

Patent

active

055545491

ABSTRACT:
An LDD type of FET, based on the salicide process, is described. It is not subject to the possibility of short circuits occurring between the source and/or the drain region and the main substrate, by way of the lightly doped layer. In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards towards the poly/silicide conductors that make connection to the source and drain areas. A process for manufacturing this structure is described. An important difference between said process and the prior art is that the oxide spacers on the outside walls (away from the gate region) of the source/drain trenches are removed prior to the formation of the heavily doped portions of the source/drain, not after it.

REFERENCES:
patent: 5053349 (1991-10-01), Matsuoka
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5278098 (1994-01-01), Wei et al.
patent: 5346860 (1994-09-01), Wei
patent: 5443996 (1995-08-01), Lee et al.
patent: 5453400 (1995-09-01), Abernathy et al.

Affiliated with

Also associated with

Rating

Salicide process for FETs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Salicide process for FETs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Salicide process for FETs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1320083