Salicide integrated solution for embedded virtual-ground memory

Details Salicide integrated solution for embedded virtual-ground memory Salicide integrated solution for embedded virtual-ground memory

2001-01-16

2003-03-11

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S283000, C438S587000, C438S595000, C438S664000

Reexamination Certificate

active

06531393

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a salicide integrated solution for embedded virtual-ground memory. More particularly, the present invention relates to an integrated solution for the processes of memory cell region and peripheral logic region in the embedded virtual-ground memory.
BACKGROUND OF THE INVENTION
A ROM is a nonvolatile memory device in which stored data are not changed in a normal operation state. A ROM is classified according to the methods for storing data into the ROM. There is a mask read only memory (MROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM) and an erasable and electrically programmable ROM (EEPROM).
The mask ROM is coded with its data, i.e., has the data stored in it, by using a specialized mask (representing particular requirement of a user) during the fabrication process. Data stored in a mask ROM is not able to be changed, rather it is only possible to read the data. One type of mask ROM causes a predetermined transistor to have a status that differs from other transistors by implanting impurity ions, so that a datum is coded. That is, the mask ROM causes a predetermined transistor to have an OFF state by implanting impurity ions during fabrication. Transistors for which impurity ions are not implanted during fabrication have an ON state, and vice versa. Therefore, the data are coded.
As illustrated in
FIG. 1
, a conventional mask ROM has a buried oxide layer
19
which is perpendicular to a wordline of poly gate
23
. A high concentration buried diffusion region made up of a common source and a drain region is provided, and is used for a bit line that is formed under the buried oxide layer
19
, so that the word line is perpendicular to the bit line. Accordingly, the word line and the bit line intersect and form transistors. The first and second transistor channels
27
and
29
are formed between the buried diffusion regions under the buried oxide layer
19
, overlapping with the poly gate
23
. The transistor T
1
having the first channel
27
that is coated with P conductivity type material maintains the OFF state, and the other transistor T
2
having the uncoated second channel
29
is not programmed and maintains the ON state.
As illustrated in
FIG. 2
, a cross-sectional view taken along section line
11
-
11
′of
FIG. 1
is shown. According to this view, a gate oxide layer
17
and a buried oxide layer
19
are formed on a P type semiconductor substrate
11
. The buried oxide layer
19
is thicker than the gate oxide layer
17
. A buried diffusion region
21
having N type impurity ions is formed under the buried oxide layer
19
. The buried diffusion region
21
is the common source/drain of the transistors, and is used for a bit line. A poly gate
23
, perpendicular to the buried diffusion region
21
, is formed on the gate oxide layer
17
. A portion of the semiconductor
11
, positioned opposite to the poly gate
23
becomes the first and second channels
27
and
29
. The transistor T
1
, having the first channel
27
, is made of the P type impurity ions and maintains the OFF state. The transistor T
2
, having the second channel
29
, maintains the ON state.
A process for forming the above-described conventional mask ROM will now be described with reference to
FIGS. 3A-3D
.
As illustrated in
FIG. 3A
, a first photosensitive layer
13
is deposited on the semiconductor substrate
11
, which is made of P type silicon. The photosensitive layer
13
is exposed to light, then developed and patterned to expose selected portions of the semiconductor substrate
11
. An N type impurity ion such as As or P is heavily doped in the semiconductor substrate
11
, using the first photosensitive layer
13
as a mask, to form an ion implanted region
15
.
As illustrated in
FIG. 3B
, the first photosensitive layer
13
is eliminated. The surface of the semiconductor substrate
11
is implanted with impurities during a thermal oxidation process, and the gate oxide layer
17
is formed on a portion where ions are not implanted. The rate of oxidation in the portion of the semiconductor substrate
11
, where the ion implanted region
15
is formed, is 15 to 20 times fastener than that of the portion where ions are not implanted due to a lattice damage, enabling the formation of a thick buried oxide layer
19
. During thermal oxidation, impurity ions in the ion implanted region
15
are activated, so that they function as the common source and drain region. The buried diffusion region
21
is used for the bit line.
As illustrated in
FIG. 3C
, impurity ions such as polycrystal silicon or CoSi are doped on the gate oxide layer
17
and the buried oxide layer
19
using chemical vapor deposition (CVD). They are patterned to be perpendicular to the buried diffusion region
21
in a photolithography method, effectively forming a wordline poly gate
23
. Therefore, a transistor is formed whose channel is the portion corresponding to the poly gate
23
between the buried diffusion regions
21
of the semiconductor substrate
11
. The second photosensitive layer
24
is deposited on the overall surface of the substrate. It is exposed to light, developed and patterned to expose the predetermined transistor. Impurity ions such as B or BF
2
are heavily implanted in the substrate to form the ion implanted region
25
, using the second photosensitive layer
24
as a mask.
As illustrated in
FIG. 3D
, the second photosensitive layer
24
is eliminated. The impurity ions in the ion implanted region
25
are heat-treated and diffused to form the first channel
27
, where P type impurity ions are heavily doped. The channel where the P type impurity ions are not doped becomes the second channel
29
. The transistor TI that is used for the first channel
27
is coded, and the other transistor T
2
that is used for the second channel
29
is not coded.
Finally, the spacers comprising the material of TEOS and SiN are formed on the sidewall of the poly gate
23
. In order to obtain a low resistivity of the poly gate
23
, the salicides are formed on the top portion of the poly gate
23
. Generally speaking, the process of forming the silicide is to deposit titanium on the poly gate
23
, and than treat it at a high temperature, such as with rapid thermal processing. After etching the titanium remaining on the poly gates
23
, the salicides of TiSi
2
are then obtained.
However, the titanium can react with silicon or polysilicon to form the salicides. In order to protect the surface of the substrate between poly gates, which will cause the connection of the buried diffusion regions by the salicides causing the damages of the mask ROM.
According to the salicide process described above, the conventional processes of the memory cell region and the peripheral logic region in the Mask ROM have to be seperated, consequently increasing the cost and processes in fabricating the Mask ROM.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a salicide integrated solution for embedded virtual-ground memory. The present invention provides the controlled distance between poly gates. In this way, the spacers formed on the side wall of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions.
It is another object of this invention to provide a salicide integrated solution for embedded virtual-ground memory. The present invention provides two dummy poly gates located on the outside poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated.
It is another object of this invention to provide a salicide integrated solution for embedded virtual-ground memory. Utilizing the present invention, the process of forming sa

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