Salicide formation process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

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438592, 438301, H01L 213205

Patent

active

060227958

ABSTRACT:
A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

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patent: 5874342 (1999-02-01), Tsai et al.
patent: 5902129 (1999-05-01), Yoshikawa et al.
Wolf et al. "Silicon processing for the VLSI era, vol. 1: Process technology" p.367, Jan. 1986.

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