Safestore frame implementation in a central processor

Details Safestore frame implementation in a central processor Safestore frame implementation in a central processor

1991-04-09

1994-01-04

Atkinson, Charles E.

Boots, shoes, and leggings

3642852, 364DIG1, 371 12, 371 165, G06F 1100

Patent

active

052768627

ABSTRACT:
In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

REFERENCES:
patent: 3783256 (1974-01-01), Caputo et al.
patent: 3784801 (1974-01-01), Caputo et al.
patent: 4697266 (1987-09-01), Finley
patent: 4703481 (1987-10-01), Fremont
patent: 4819154 (1989-04-01), Stiffler
patent: 4853932 (1989-08-01), Nitschke et al.
patent: 4930128 (1989-08-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Safestore frame implementation in a central processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Safestore frame implementation in a central processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Safestore frame implementation in a central processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-315564